diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 874ea19..2dec218 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -224,8 +224,44 @@ with BackBoardSlvIn{
 
 
 
+trait BackBoardSlvOut16{ this: BackBoardSlvLocal =>
+
+  val outReg  = RegInit(0.U(16.W))
+  val chsWire = Wire( Vec(16, UInt(2.W)) )
+
+  val mthodReg = RegInit(0.U(16.W))
+  val valueReg = RegInit(0.U(16.W))
+
+  val outPin = Wire(UInt(16.W))
+
+  outPin := 
+    Mux(statusPR === 3.U, outReg, (mthodReg & valueReg) | (~mthodReg & outReg))
+
+}
 
 
+class DOut16 extends BackBoardSlvLocal
+with BackBoardSlvStatusPR
+with BackBoardSlvOut16{
+  val out = IO(Output(UInt(16.W)))
+
+  when( isCrcPass & downRegTemp(0)(3,0) === 0.U ){
+    outReg := Cat(downRegTemp(3), downRegTemp(2))
+  }
+  when( isCrcPass & downRegTemp(0)(3,0) === 1.U ){
+    mthodReg := Cat(downRegTemp(3), downRegTemp(2))
+    valueReg := Cat(downRegTemp(5), downRegTemp(4))
+  }
+
+  when( statusPage === 0.U ){
+    upReg(4) := Cat( ( 3  to 0  by -1).map{ i => chsWire(i) } )
+    upReg(5) := Cat( ( 7  to 4  by -1).map{ i => chsWire(i) } )
+    upReg(6) := Cat( ( 11 to 8  by -1).map{ i => chsWire(i) } )
+    upReg(7) := Cat( ( 15 to 12 by -1).map{ i => chsWire(i) } )
+  }
+
+
+}
 
 // class BackBoardSlvOut16 extends BackBoardSlvLocal{
 //   val in  = IO(Input(UInt(32.W)))