diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index a331cfe..3f070b0 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -56,6 +56,8 @@ class BackBoardMstBase extends Module{ //10M
   val ctrlSynch    = RegInit( false.B )
   val ctrlInit     = RegInit( false.B )
 
+  val ctrlFun = RegInit(0.U(8.W))
+
   val slvNum  = RegInit(0.U(6.W))
   val slvOffLine = RegInit(0.U(6.W))
   val linkNum = RegInit(0.U(7.W))
@@ -139,15 +141,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
           statusSynch  ,
           statusInit
         ),
-      ( activeAddr === 1.U) -> 
-        Cat(
-          ctrlTransmit,
-          0.U(1.W),
-          0.U(1.W),
-          0.U(1.W),
-          ctrlSynch,
-          ctrlInit
-        ),
+      ( activeAddr === 1.U) -> ctrlFun,
       ( activeAddr === 2.U) -> slvNum,
       ( activeAddr === 3.U) -> slvOffLine,
       ( activeAddr === 4.U) -> testReg,
@@ -173,7 +167,20 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
   //10M
   when(~RegNext( io.testIO, false.B ) & io.testIO){
-    ctrlTransmit := true.B
+    when( ctrlFun === 0.U ){
+      statusInit := false.B
+      ctrlInit   := true.B
+    }
+
+    when( ctrlFun === 1.U ){
+      statusSynch := false.B
+      ctrlSynch   := true.B
+    }
+
+    when( ctrlFun === 5.U ){
+      ctrlTransmit := true.B      
+    }
+
   }
 
 
@@ -198,16 +205,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
 
 
     when( wrRegAddr === 1.U ){
-      // ctrlTransmit := wrRegData.extract(5)
-
-      ctrlSynch    := wrRegData.extract(1)
-
-      when( wrRegData.extract(0) ){
-        ctrlInit     := true.B
-        statusSynch   := false.B
-        statusInit    := false.B        
-      }
-
+      ctrlFun := wrRegData
     }
 
     when( wrRegAddr === 2.U ){