try RoCC
hack 入，但io如何扇出到顶层？ Revert "hack 入，但io如何扇出到顶层？" This reverts commit 04dd4dff462b8986d18d13ee7c6b3f17caad247c. Revert "Revert "hack 入，但io如何扇出到顶层？"" This reverts commit a2fadc0e5524cd292ed245f1fbb5f4a688d95a1d. CDRIN成功扇出 Rocc仿真环境 扇出RoCC请求返回的FIFO Revert "扇出RoCC请求返回的FIFO" This reverts commit c52777091403d300f19935df7b6de3d62c57430b. RoCC请求返回FIFO使用FLOW模式
This commit is contained in:
Ruige Lee (WSL)
555
src/main/scala/backBoard/ebus/RoCC2CDR.scala
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555
src/main/scala/backBoard/ebus/RoCC2CDR.scala
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@@ -0,0 +1,555 @@
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package BACK
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import chisel3._
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import chisel3.util._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.tile._
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class RocCC2CDRInIO extends Bundle{
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val overCLK = Bool()
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val dDatIn = Bool()
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val uDatIn = Bool()
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val isLast = Bool()
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}
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class RocCC2CDROutIO extends Bundle{
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val dDatOut = Bool()
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val uDatOut = Bool()
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val isOnline = Bool()
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}
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class RoCC2CDRIO extends Bundle{
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val overCLK = Input(Bool())
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val dDatIn = Input(Bool())
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val dDatOut = Output(Bool())
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val uDatIn = Input(Bool())
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val uDatOut = Output(Bool())
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val isOnline = Output(Bool())
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val isLast = Input(Bool())
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}
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class RoCC2CDR()(implicit p: Parameters) extends LazyModule {
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val opcodes: OpcodeSet = OpcodeSet.custom0
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val roccCSRs: Seq[CustomCSR] = Nil
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lazy val module: RoCC2CDRImpl = new RoCC2CDRImpl(this)
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}
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abstract class RoCC2CDRImplBase(outer: RoCC2CDR)(implicit p: Parameters) extends LazyModuleImp(outer) {
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val io = IO(new RoCCIO(0, 0))
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// val cdrio: RoCC2CDRIO = IO(new RoCC2CDRIO)
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val cdrInio = IO(Input(new RocCC2CDRInIO))
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val cdrOutio = IO(Output(new RocCC2CDROutIO))
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val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
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CDRIn(0).io.serDat := cdrInio.dDatIn
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CDRIn(1).io.serDat := cdrInio.uDatIn
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CDRIn(0).io.overCLK := cdrInio.overCLK
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CDRIn(1).io.overCLK := cdrInio.overCLK
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val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
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cdrOutio.dDatOut := CDROut(0).io.serDat
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cdrOutio.uDatOut := CDROut(1).io.serDat
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val txFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) }
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val rxFifo = for( i <- 0 until 2 ) yield { Module(new Queue(UInt(32.W), 16)) }
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val isTLWriteSoftReset = for( i <- 0 until 4 ) yield { Wire(Bool()) }
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val isTLReadStatus = Wire( Bool() )
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val txLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) }
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val rxLeft = for( i <- 0 until 2 ) yield { RegInit(0.U(5.W)) }
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val wdata = Wire(UInt(32.W))
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}
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trait RoCC2CDRImplTx{ this: RoCC2CDRImplBase =>
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val isTLWriteTxLen = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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val isTLWriteTxFifo = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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val isTxFifoRelease = for( i <- 0 until 2 ) yield { Wire( Bool()) }
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val txLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) }
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val isTxBusy = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isTxFull = for( i <- 0 until 2 ) yield { ~txFifo(i).io.enq.ready }
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val intTxFifoFull = for( i <- 0 until 2 ) yield { ~RegNext(isTxFull(i), false.B) & isTxFull(i) }
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val intTxFinish = for( i <- 0 until 2 ) yield { CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast }
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val intTxEnd = for( i <- 0 until 2 ) yield { ShiftRegister( intTxFinish(i), 6, false.B, true.B) }
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val intTxFifoDeq = for( i <- 0 until 2 ) yield { txFifo(i).io.deq.fire }
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val txCnt = for( i <- 0 until 2 ) yield { Reg(UInt(2.W)) }
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val txData = for( i <- 0 until 2 ) yield { Reg(UInt(32.W)) }
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for( i <- 0 until 2 ) {
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when( txFifo(i).io.deq.fire ){ //txCnt(i) === 3.U
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txData(i) := txFifo(i).io.deq.bits
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when( isTxBusy(i) ){
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assert(CDROut(i).io.axis.fire)
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}
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} .elsewhen( CDROut(i).io.axis.fire ){
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txData(i) := txData(i) << 8
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}
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txFifo(i).io.deq.ready :=
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isTxFifoRelease(i) & Mux( isTxBusy(i), CDROut(i).io.axis.fire & txCnt(i) === 3.U, true.B )
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txFifo(i).reset := reset.asBool | isTLWriteSoftReset(0+i)
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CDROut(i).reset := reset.asBool | isTLWriteSoftReset(0+i)
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CDROut(i).io.axis.bits.tdata := txData(i).head(8)
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CDROut(i).io.axis.bits.tlast := ~txFifo(i).io.deq.valid & txCnt(i) === 3.U
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CDROut(i).io.axis.bits.tuser := false.B
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CDROut(i).io.axis.valid := isTxBusy(i)
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when( isTLWriteSoftReset(i) ){
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isTxBusy(i) := false.B
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}.elsewhen( txFifo(i).io.deq.fire & ~isTxBusy(i) ){
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isTxBusy(i) := true.B
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} .elsewhen( CDROut(i).io.axis.fire & CDROut(i).io.axis.bits.tlast ){
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isTxBusy(i) := false.B
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}
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when( isTLWriteSoftReset(0+i) ){
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txCnt(i) := 0.U
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} .elsewhen( CDROut(i).io.axis.fire ){
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txCnt(i) := txCnt(i) + 1.U
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}
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when( isTLWriteTxLen(i) ){
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txLen(i) := wdata
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} .elsewhen( CDROut(i).io.axis.fire ){
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txLen(i) := txLen(i) - 1.U
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}
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txFifo(i).io.enq.bits := wdata
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txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U
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when( isTLWriteSoftReset(0+i) ){
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txLeft(i) := 0.U
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} .elsewhen( txFifo(i).io.enq.fire & txFifo(i).io.deq.fire ){
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txLeft(i) := txLeft(i)
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} .elsewhen( txFifo(i).io.enq.fire ){
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txLeft(i) := txLeft(i) + 1.U
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} .elsewhen( txFifo(i).io.deq.fire ){
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txLeft(i) := txLeft(i) - 1.U
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}
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}
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}
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trait RoCC2CDRImplRx{ this: RoCC2CDRImplBase =>
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val isTLReadRxLen = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLReadRxFifo = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val rxLen = for( i <- 0 until 2 ) yield { RegInit(0.U(12.W)) }
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val isRxValid = for( i <- 0 until 2 ) yield { rxFifo(i).io.deq.valid }
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val isRxError = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isAxisEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val isRxEnd = for( i <- 0 until 2 ) yield { isAxisEnd(i) & ~rxFifo(i).io.deq.valid }
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val intRxError = for( i <- 0 until 2 ) yield { ~RegNext(isRxError(i), false.B) & isRxError(i) }
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val intRxStart = for( i <- 0 until 2 ) yield { rxLen(i) === 0.U & CDRIn(i).io.axis.fire }
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val intRxEnd = for( i <- 0 until 2 ) yield { ~RegNext(isRxEnd(i), false.B) & isRxEnd(i) }
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val intRxFifoEnq = for( i <- 0 until 2 ) yield { rxFifo(i).io.enq.fire }
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val rxCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(2.W)) }
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val rxData = for( i <- 0 until 2 ) yield { Reg(UInt(24.W)) }
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for( i <- 0 until 2 ) {
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when( isTLWriteSoftReset(2+i) ){
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isAxisEnd(i) := false.B
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} .elsewhen( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast ){
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isAxisEnd(i) := true.B
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}
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when( isTLWriteSoftReset(2+i) ){
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rxCnt(i) := 0.U
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} .elsewhen( CDRIn(i).io.axis.fire ){
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rxCnt(i) := rxCnt(i) + 1.U
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rxData(i) := Cat( rxData(i), CDRIn(i).io.axis.bits.tdata )
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}
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when( isTLWriteSoftReset(2+i) ){
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rxLen(i) := 0.U
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} .elsewhen( CDRIn(i).io.axis.fire ){
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rxLen(i) := rxLen(i) + 1.U
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}
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rxFifo(i).io.enq.valid := CDRIn(i).io.axis.fire & rxCnt(i) === 3.U
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rxFifo(i).io.enq.bits := Cat( rxData(i)(23, 0) , CDRIn(i).io.axis.bits.tdata )
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assert( ~(( CDRIn(i).io.axis.fire & CDRIn(i).io.axis.bits.tlast) & rxCnt(i) =/= 3.U), "Assert Failed! Rx must 4-byte Align!" )
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CDRIn(i).io.axis.ready := true.B
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rxFifo(i).reset := reset.asBool | isTLWriteSoftReset(2+i)
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CDRIn(i).reset := reset.asBool | isTLWriteSoftReset(2+i)
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rxFifo(i).io.deq.ready := isTLReadRxFifo(i)
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when( isTLWriteSoftReset(2+i) ){
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isRxError(i) := false.B
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} .elsewhen( rxFifo(i).io.enq.valid & ~rxFifo(i).io.enq.ready ){
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isRxError(i) := true.B
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printf(s"Warning, RxFifo$i Overflow!\n")
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}
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when( isTLWriteSoftReset(2+i) ){
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rxLeft(i) := 0.U
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} .elsewhen( rxFifo(i).io.enq.fire & rxFifo(i).io.deq.fire ){
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rxLeft(i) := rxLeft(i)
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} .elsewhen( rxFifo(i).io.enq.fire ){
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rxLeft(i) := rxLeft(i) + 1.U
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} .elsewhen( rxFifo(i).io.deq.fire ){
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rxLeft(i) := rxLeft(i) - 1.U
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}
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}
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}
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trait RoCC2CDRImplIsLast{ this: RoCC2CDRImplBase =>
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cdrOutio.isOnline := false.B
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val isReadIsLast = Wire(Bool())
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}
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trait RoCC2CDRImplUserCRC{ this: RoCC2CDRImplBase =>
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val isTLWriteTxFifo: Seq[Bool]
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val isTLReadRxFifo: Seq[Bool]
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val isTLReadTxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLReadRxCrc = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val txCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) }
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val rxCrc = for( i <- 0 until 2 ) yield { Module(new crc32_32) }
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for( i <- 0 until 2 ) {
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txCrc(i).io.enq.valid := isTLWriteTxFifo(i)
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txCrc(i).io.enq.bits := wdata
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rxCrc(i).io.enq.valid := isTLReadRxFifo(i)
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rxCrc(i).io.enq.bits := rxFifo(i).io.deq.bits
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txCrc(i).reset := reset.asBool | isTLWriteSoftReset(0+i)
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rxCrc(i).reset := reset.asBool | isTLWriteSoftReset(2+i)
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}
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}
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trait RoCC2CDRImplLimitTimmer{ this: RoCC2CDRImplBase =>
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val intRxStart: Seq[Bool]
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val isTLWriteSoftReset: Seq[Bool]
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val isTxFifoRelease: Seq[Bool]
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val isTLWriteLimitTimerAim = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val isTLWriteLimitTxPair = for( i <- 0 until 2 ) yield { Wire(Bool()) }
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val limitTimerCnt = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) }
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val limitTimerAim = for( i <- 0 until 2 ) yield { RegInit(0.U(16.W)) }
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val isLimitTimerTrigger = for( i <- 0 until 2 ) yield { RegInit(false.B) }
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val txPairSel = for( i <- 0 until 2 ) yield { RegInit((i.U)(2.W)) }
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for( i <- 0 until 2 ){
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when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){
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limitTimerCnt(i) := 0.U
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} .elsewhen( limitTimerCnt(i) =/= limitTimerAim(i) ){
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when( isLimitTimerTrigger(i) ){
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limitTimerCnt(i) := limitTimerCnt(i) + 1.U
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}
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}
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when( isTLWriteLimitTimerAim(i) ){
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limitTimerAim(i) := wdata
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}
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when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){
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isLimitTimerTrigger(i) := false.B
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} .elsewhen( intRxStart(i) ){
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isLimitTimerTrigger(i) := true.B
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}
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when( isTLWriteSoftReset(0+i) | isTLWriteSoftReset(2+i) ){
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txPairSel(i) := i.U
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} .elsewhen( isTLWriteLimitTxPair(i) ){
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txPairSel(i) := wdata
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}
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isTxFifoRelease(i) := ( 0 until 2).map{ lmt =>
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((txPairSel(lmt) =/= i.U) | (limitTimerCnt(lmt) === limitTimerAim(lmt)))
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}.reduce(_&_)
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}
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}
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class RoCC2CDRImpl(outer: RoCC2CDR)(implicit p: Parameters) extends RoCC2CDRImplBase(outer)
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with RoCC2CDRImplTx with RoCC2CDRImplRx
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with RoCC2CDRImplIsLast
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with RoCC2CDRImplUserCRC
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with RoCC2CDRImplLimitTimmer
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{
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io.mem.req.valid := false.B
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io.mem.req.bits := DontCare
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io.mem.s1_kill := false.B
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io.mem.s1_data := DontCare
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io.mem.s2_kill := false.B
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io.mem.keep_clock_enabled := false.B
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// io.interrupt = Output(Bool())
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// io.exception = Input(Bool())
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io.fpu_req.valid := false.B
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io.fpu_req.bits := DontCare
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io.fpu_resp.ready := true.B
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isTLWriteSoftReset(0) := io.cmd.fire & io.cmd.bits.inst.funct === 0.U
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isTLWriteTxLen(0) := io.cmd.fire & io.cmd.bits.inst.funct === 1.U
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isTLWriteTxFifo(0) := io.cmd.fire & io.cmd.bits.inst.funct === 2.U
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isTLReadTxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 3.U
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isTLWriteSoftReset(1) := io.cmd.fire & io.cmd.bits.inst.funct === 4.U
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isTLWriteTxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 5.U
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isTLWriteTxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 6.U
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isTLReadTxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 7.U
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isTLWriteSoftReset(2) := io.cmd.fire & io.cmd.bits.inst.funct === 8.U
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isTLReadRxLen(0) := io.cmd.fire & io.cmd.bits.inst.funct === 9.U
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isTLReadRxFifo(0) := io.cmd.fire & io.cmd.bits.inst.funct === 10.U
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isTLReadRxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 11.U
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isTLWriteLimitTimerAim(0) := io.cmd.fire & io.cmd.bits.inst.funct === 12.U
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isTLWriteLimitTxPair(0) := io.cmd.fire & io.cmd.bits.inst.funct === 13.U
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isTLWriteSoftReset(3) := io.cmd.fire & io.cmd.bits.inst.funct === 14.U
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isTLReadRxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 15.U
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isTLReadRxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 16.U
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isTLReadRxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 17.U
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isTLWriteLimitTimerAim(1) := io.cmd.fire & io.cmd.bits.inst.funct === 18.U
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isTLWriteLimitTxPair(1) := io.cmd.fire & io.cmd.bits.inst.funct === 19.U
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isTLReadStatus := io.cmd.fire & io.cmd.bits.inst.funct === 20.U
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isReadIsLast := io.cmd.fire & io.cmd.bits.inst.funct === 21.U
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// int(0) := intTxEnd(0)
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// int(1) := intTxEnd(1)
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|
||||
// int(2) := intRxError(0)
|
||||
// int(3) := intRxError(1)
|
||||
|
||||
// int(4) := intRxStart(0)
|
||||
// int(5) := intRxStart(1)
|
||||
|
||||
// int(6) := intRxEnd(0)
|
||||
// int(7) := intRxEnd(1)
|
||||
|
||||
// int(8) := intTxFifoDeq(0)
|
||||
// int(9) := intTxFifoDeq(1)
|
||||
|
||||
// int(10) := intRxFifoEnq(0)
|
||||
// int(11) := intRxFifoEnq(1)
|
||||
|
||||
io.interrupt :=
|
||||
intTxEnd(0) |
|
||||
intTxEnd(1) |
|
||||
intRxError(0) |
|
||||
intRxError(1) |
|
||||
intRxStart(0) |
|
||||
intRxStart(1) |
|
||||
intRxEnd(0) |
|
||||
intRxEnd(1) |
|
||||
intTxFifoDeq(0) |
|
||||
intTxFifoDeq(1) |
|
||||
intRxFifoEnq(0) |
|
||||
intRxFifoEnq(1)
|
||||
|
||||
wdata := io.cmd.bits.rs1
|
||||
|
||||
val cmdInfo = RegEnable(io.cmd.bits, io.cmd.fire)
|
||||
val rdata = Reg(UInt(32.W))
|
||||
|
||||
|
||||
// val cmdReady = RegInit(true.B)
|
||||
val respValid = RegInit(false.B)
|
||||
|
||||
io.busy := respValid
|
||||
io.cmd.ready := ~respValid
|
||||
|
||||
io.resp.valid := respValid
|
||||
io.resp.bits.rd := cmdInfo.inst.rd
|
||||
|
||||
io.resp.bits.data := rdata
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
printf("Warning, no protection on tx rx fifo!\n")
|
||||
// MuxCase( true.B, Array(
|
||||
// ( io.cmd.bits.inst.funct === 2.U ) -> txFifo(0).io.enq.ready,
|
||||
// ( io.cmd.bits.inst.funct === 6.U ) -> txFifo(1).io.enq.ready,
|
||||
// ( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid,
|
||||
// ( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid,
|
||||
// ))
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
when( isTLReadStatus ){
|
||||
rdata := Cat( txLeft(1), txLeft(0), rxLeft(1), rxLeft(0), isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), isTxBusy(1), isTxBusy(0), isTxFull(1), isTxFull(0) )
|
||||
} .elsewhen(isTLReadRxLen(0) ){
|
||||
rdata := rxLen(0)
|
||||
} .elsewhen(isTLReadRxLen(1) ){
|
||||
rdata := rxLen(1)
|
||||
} .elsewhen(isTLReadRxFifo(0) ){
|
||||
rdata := rxFifo(0).io.deq.bits
|
||||
} .elsewhen(isTLReadRxFifo(1) ){
|
||||
rdata := rxFifo(1).io.deq.bits
|
||||
} .elsewhen(isReadIsLast){
|
||||
rdata := cdrInio.isLast
|
||||
} .elsewhen(isTLReadTxCrc(0)){
|
||||
rdata := txCrc(0).io.crc
|
||||
} .elsewhen(isTLReadTxCrc(1)){
|
||||
rdata := txCrc(1).io.crc
|
||||
} .elsewhen(isTLReadRxCrc(0)){
|
||||
rdata := rxCrc(0).io.crc
|
||||
} .elsewhen(isTLReadRxCrc(1)){
|
||||
rdata := rxCrc(1).io.crc
|
||||
}
|
||||
|
||||
when( io.resp.fire ){ //允许连续触发
|
||||
respValid := false.B
|
||||
} .elsewhen( isTLReadStatus ){
|
||||
respValid := true.B
|
||||
} .elsewhen(isTLReadRxLen(0) ){
|
||||
respValid := true.B
|
||||
} .elsewhen(isTLReadRxLen(1) ){
|
||||
respValid := true.B
|
||||
} .elsewhen(isTLReadRxFifo(0) ){
|
||||
respValid := true.B
|
||||
} .elsewhen(isTLReadRxFifo(1) ){
|
||||
respValid := true.B
|
||||
} .elsewhen(isReadIsLast){
|
||||
respValid := true.B
|
||||
} .elsewhen(isTLReadTxCrc(0)){
|
||||
respValid := true.B
|
||||
} .elsewhen(isTLReadTxCrc(1)){
|
||||
respValid := true.B
|
||||
} .elsewhen(isTLReadRxCrc(0)){
|
||||
respValid := true.B
|
||||
} .elsewhen(isTLReadRxCrc(1)){
|
||||
respValid := true.B
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
trait HasLazyRoCC2CDR { this: BaseTile =>
|
||||
val roccs = LazyModule(new RoCC2CDR())
|
||||
|
||||
val roccCSRs = Seq(roccs.roccCSRs) // the set of custom CSRs requested by all roccs
|
||||
}
|
||||
|
||||
trait HasLazyRoCC2CDRModule extends HasCoreParameters { this: RocketTileModuleImp with HasFpuOpt =>
|
||||
|
||||
// val (respArb, cmdRouter) = {
|
||||
// val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size))
|
||||
val cmdRouter = Module(new Queue( new RoCCCommand, 2, false, true ))//Module(new RoccCommandRouter( Seq(outer.roccs.opcodes) )(outer.p))
|
||||
|
||||
// outer.roccs.module.io.ptw ++=: ptwPorts
|
||||
outer.roccs.module.io.cmd <> cmdRouter.io.deq
|
||||
// val dcIF = Module(new SimpleHellaCacheIF()(outer.p))
|
||||
// dcIF.io.requestor <> outer.roccs.module.io.mem
|
||||
// dcachePorts += dcIF.io.cache
|
||||
//respArb.io.in(0) <> Queue(outer.roccs.module.io.resp)
|
||||
|
||||
|
||||
fpuOpt foreach { fpu =>
|
||||
fpu.io.cp_req.valid := false.B
|
||||
fpu.io.cp_resp.ready := false.B
|
||||
}
|
||||
|
||||
// (Some(respArb), Some(cmdRouter))
|
||||
// }
|
||||
|
||||
// val roccCSRIOs = Seq(outer.roccs.module.io.csrs)
|
||||
|
||||
// (core.io.rocc.csrs zip roccCSRIOs.flatten).foreach { t => t._2 := t._1 }
|
||||
|
||||
val cdrInio = IO(Input(new RocCC2CDRInIO))
|
||||
val cdrOutio = IO(Output(new RocCC2CDROutIO))
|
||||
|
||||
// val cdrio: RoCC2CDRIO = IO(new RoCC2CDRIO)
|
||||
// dontTouch(cdrio)
|
||||
|
||||
|
||||
cdrInio <> outer.roccs.module.cdrInio
|
||||
cdrOutio <> outer.roccs.module.cdrOutio
|
||||
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user