Merge branch 'mp_eb_dev' into feature/dwupEx

Makefile

@@ -53,6 +53,18 @@ testShin:
 	vvp  -N ./tb/build/shinTest.iverilog -lxt2 || true
 	./tb/shinTest/check_testcase.py
 
+testCDR:
+	iverilog -Wall  \
+	-o ./tb/build/simCDR.iverilog  \
+	-y ./generated/shin \
+	-y ./generated/SimCDR \
+	-I ./generated/SimCDR \
+	-I ./generated/shin \
+	-D RANDOMIZE_REG_INIT \
+	./tb/shinTest/SimCDRTb.v 
+	vvp  -N ./tb/build/simCDR.iverilog -lxt2
+
+
 testFilter:
 	./tb/shinTest/test_filter.py
 

src/main/scala/backBoard/shin/Interface.scala

@@ -810,10 +810,10 @@ trait InterfaceSync{ this: InterfaceBase =>
     }
 
     for( i <- 0 until 4 ){
-      when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
+      when( addrw === ("h122".U(16.W) + (2*i).U)){
-        syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) 
+        syncWidth(i) := Cat( syncWidth(i)(15,8), dataw ) 
-      } .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
+      } .elsewhen( addrw === ("h123".U(16.W) + (2*i).U) ){
-        syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) 
+        syncWidth(i) := Cat( dataw, syncWidth(i)(7,0) ) 
       }
     }
 
@@ -992,13 +992,18 @@ trait InterfaceSync{ this: InterfaceBase =>
 
   when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
     syncSign(0) := true.B
-    syncPoint := syncPoint + cReg.syncPeroid
+    
   } .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
     syncSign(0) := false.B
   } .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
     syncSign(0) := false.B
   }
 
+  when( cReg.syncPoint <= cReg.recoTimeStamp ){
+    syncPoint := syncPoint + cReg.syncPeroid
+  }
+
+
   for( i <- 1 until 4 ) {
 
     when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
@@ -1200,12 +1205,17 @@ trait InterfaceSystem{ this: InterfaceBase =>
     intStatus(19) := true.B
   }
 
+
+  val intHWErr = Seq(
+   ( ~RegNext(io.intHWTrig(0), false.B) & io.intHWTrig(0)),
+   ( ~RegNext(io.intHWTrig(1), false.B) & io.intHWTrig(1))
+  )
   //下行接收硬件错误
-  when( io.intHWTrig(0) ){
+  when( intHWErr(0) ){
     intStatus(29) := true.B
   }
   //上行接收硬件错误
-  when( io.intHWTrig(1) ){
+  when( intHWErr(1) ){
     intStatus(30) := true.B
   }
 
@@ -1241,8 +1251,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
     (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
     (0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
     isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生
-    io.intHWTrig(0) | //下行接收硬件错误
+    intHWErr(0) | //下行接收硬件错误
-    io.intHWTrig(1)   //上行接收硬件错误
+    intHWErr(1)   //上行接收硬件错误
 
   when( intPulseResetCnt === intPulseWidth ){
     intPulse := false.B

src/main/scala/backBoard/shin/MasterParser.scala

@@ -114,14 +114,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
   io.downOut.bits.tdata := Mux1H(Seq(
     ( txCnt  <  txLen       ) -> 
       MuxCase( io.sram_r.datar, Array(
-        ( isRplTimeStamp  & ( txCnt === rplCnt0  ) ) -> io.cReg.timeStamp(7,0),
+        ( isRplTimeStamp  & ( txCnt === rplCnt0  ) ) -> RegEnable(io.cReg.timeStamp(7,0),   io.downOut.fire & txCnt === 0.U ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt1  ) ) -> RegEnable(io.cReg.timeStamp(15,8),  io.downOut.fire & txCnt === rplCnt0 ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt1  ) ) -> RegEnable(io.cReg.timeStamp(15,8),  io.downOut.fire & txCnt === 0.U ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt2  ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === rplCnt0 ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt2  ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === 0.U ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt3  ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === rplCnt0 ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt3  ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === 0.U ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt4  ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === rplCnt0 ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt4  ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === 0.U ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt5  ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === rplCnt0 ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt5  ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === 0.U ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt6  ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === rplCnt0 ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt6  ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === 0.U ),
-        ( isRplTimeStamp  & ( txCnt === rplCnt7  ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === rplCnt0 ),
+        ( isRplTimeStamp  & ( txCnt === rplCnt7  ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === 0.U ),
         ( isRplDeltaStamp & ( txCnt === rplCnt8  ) ) -> io.cReg.mstDeltaTime(7,0),
         ( isRplDeltaStamp & ( txCnt === rplCnt9  ) ) -> io.cReg.mstDeltaTime(15,8),
         ( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),

src/test/scala/SimCDR.scala

@@ -0,0 +1,77 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+class SimCDR extends Module with RequireAsyncReset{
+  val io = IO(new Bundle{
+    val data = Input( UInt(8.W) )
+
+    val multiCLK = Input(Vec(16, Bool()))
+
+    val flush = Input(Bool())
+
+    val isSuccess = Output(Bool())
+    val isFailed = Output(Bool())
+  })
+
+
+
+
+  val cdrIn = Module(new MPCDRIn)
+  val cdrOut = Module(new CDROut)
+  val record = Module( new Queue(UInt(8.W), 256) )
+
+  val dataCnt = RegInit(0.U(12.W))
+  val payloadLen = RegInit(("hFFF".U)(12.W))
+
+   
+  when( cdrOut.io.axis.fire & dataCnt === 0.U ){
+    payloadLen := Cat( io.data, 0.U(4.W) )
+  } .elsewhen( cdrOut.io.axis.fire & dataCnt === 1.U ){
+    payloadLen := Cat( payloadLen(11,4), io.data(7,4) ) + 4.U + 4.U
+  }
+
+  when( cdrOut.io.axis.fire ){
+    when( dataCnt >= payloadLen - 1.U ){
+      dataCnt := 0.U
+    } .otherwise{
+      dataCnt := dataCnt + 1.U
+    }
+  }
+
+
+  cdrOut.io.flush := io.flush
+
+  cdrIn.clock := io.multiCLK(0).asClock
+  cdrIn.io.flush := io.flush
+  cdrIn.multiCLK := io.multiCLK
+
+  cdrIn.io.serDat := cdrOut.io.serDat
+
+  assert( ~(record.io.enq.valid  & ~record.io.enq.ready), "Assert Failed, Warning, fifo overflow!\n" )
+  assert( ~(~record.io.deq.valid & record.io.deq.ready),  "Assert Failed, Warning, fifo underflow!\n" )
+
+  val isTxEnd = cdrOut.io.axis.fire & cdrOut.io.axis.bits.tlast
+
+  cdrOut.io.axis.valid := ~io.flush & ShiftRegisters( ~isTxEnd, 16 ).reduce(_&_)
+  cdrOut.io.axis.bits.tdata  := io.data
+  cdrOut.io.axis.bits.tuser  := false.B
+  cdrOut.io.axis.bits.tlast  := dataCnt === (payloadLen - 1.U)
+
+
+
+  record.io.enq.valid := cdrOut.io.axis.fire
+  record.io.enq.bits  := io.data
+
+  record.io.deq.ready := cdrIn.io.axis.fire
+  cdrIn.io.axis.ready := true.B
+
+  io.isFailed  := cdrIn.io.axis.fire & (record.io.deq.bits =/= cdrIn.io.axis.bits.tdata)
+  io.isSuccess := cdrIn.io.axis.fire & cdrIn.io.axis.bits.tlast
+
+}
+
+

src/test/scala/gcd/test.scala

@@ -103,6 +103,11 @@ object testShinModule extends App {
       ChiselGeneratorAnnotation(() => { new ShinTop }),
     ))
 
+  (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/SimCDR/", "-e", "verilog" ) ++ args, Seq(
+      ChiselGeneratorAnnotation(() => { new SimCDR }),
+    ))
+    
+
 
 }
 

tb/shinTest/SimCDRTb.v

@@ -0,0 +1,96 @@
+`timescale 1 ns / 1 ps
+
+
+module SimCDRTb(
+
+);
+
+    reg clock = 0;
+    reg reset = 0;
+
+    reg [15:0] multiCLK;
+
+    initial begin
+        clock = 0;
+        reset = 1;
+
+        #100
+        reset <= 1;
+
+        #240
+        reset <= 0;
+    end
+
+
+    initial begin
+        forever begin #80 clock <= ~clock; end
+    end
+
+    generate
+    for( genvar i = 0; i < 16; i = i + 1 ) begin
+        initial begin
+        multiCLK[i] = 0;
+        for( integer j = 0; j < i; j = j + 1 ) begin
+            #20
+            ;
+        end
+        forever begin #80 multiCLK[i] <= ~multiCLK[i]; end
+        end
+    end  
+    endgenerate
+
+    reg [7:0] data;
+    wire success;
+    wire failed;
+
+    always @(posedge clock) begin
+        data <= $random;
+    end
+
+
+    SimCDR s_SimCDR(
+        .clock(clock),
+        .reset(reset),
+        .io_data(data),
+        .io_multiCLK_0(multiCLK[0]),
+        .io_multiCLK_1(multiCLK[1]),
+        .io_multiCLK_2(multiCLK[2]),
+        .io_multiCLK_3(multiCLK[3]),
+        .io_multiCLK_4(multiCLK[4]),
+        .io_multiCLK_5(multiCLK[5]),
+        .io_multiCLK_6(multiCLK[6]),
+        .io_multiCLK_7(multiCLK[7]),
+        .io_multiCLK_8(multiCLK[8]),
+        .io_multiCLK_9(multiCLK[9]),
+        .io_multiCLK_10(multiCLK[10]),
+        .io_multiCLK_11(multiCLK[11]),
+        .io_multiCLK_12(multiCLK[12]),
+        .io_multiCLK_13(multiCLK[13]),
+        .io_multiCLK_14(multiCLK[14]),
+        .io_multiCLK_15(multiCLK[15]),
+
+        .io_flush(1'b0),
+        .io_isSuccess(success),
+        .io_isFailed(failed)
+    );
+
+
+    initial
+    begin
+        $dumpfile("./tb/build/wave_cdr.vcd"); //生成的vcd文件名称
+        $dumpvars(0, SimCDRTb);//tb模块名称
+    end
+
+    always @(posedge clock) begin
+        if (success) begin
+            $display("Success onces! \n");
+        end
+        if (failed) begin
+            $display("Error! \n");
+            $stop;
+        end
+    end
+
+
+
+endmodule

tb/shinTest/gen_pkt.py

@@ -40,19 +40,20 @@ if __name__ == '__main__':
     #add_tc_2_runlist(base.tc24())
     #add_tc_2_runlist(base.tc25())
     #add_tc_2_runlist(base.tc26())
+    #add_tc_2_runlist(base.tc27())
 
     #add_tc_2_runlist(broadcast.tc1())
     #add_tc_2_runlist(broadcast.tc2())
     #add_tc_2_runlist(broadcast.tc3())
 
     
-    add_tc_2_runlist(sync.tc1())
+    #add_tc_2_runlist(sync.tc1())
-    add_tc_2_runlist(sync.tc2())
+    #add_tc_2_runlist(sync.tc2())
-    add_tc_2_runlist(sync.tc3())
+    #add_tc_2_runlist(sync.tc3())
     #add_tc_2_runlist(sync.tc4())
     #add_tc_2_runlist(sync.tc5())
     #add_tc_2_runlist(sync.tc6())
-    #add_tc_2_runlist(sync.tc7())
+    add_tc_2_runlist(sync.tc7())
     
 
     

tb/shinTest/testcase/base.py

@@ -1815,3 +1815,151 @@ def tc26():
 
     return gen_file_def
 
+def tc27():
+    genPkt = GenPkt()
+
+    gen_file_def = "base_tc27"
+    sm_idx = 0
+    tc_des = "测试主站并行输出。在SM0工作的情况下，操作SM1，SM2，SM3，然后看是否正常。\\n" 
+    
+
+    #-------------------------------------------------------------------------
+    #>>>>>>普通数据包 sm1，2个读 
+    genPkt.clean()
+    genPkt.setPktType(0)
+    
+    #subPkt参数：索引、索引类型、地址、命令、长度、数据
+    genPkt.addSubPkt(0x01, 0, 0x302, 0x1, 2, [0x00, 0x03])
+    genPkt.addSubPkt(0x02, 0, 0x302, 0x1, 2, [0x00, 0x01])
+    genPkt.addSubPkt(0x03, 0, 0x302, 0x1, 2, [0x00, 0x01])
+    genPkt.addSubPkt(0x04, 0, 0x302, 0x1, 2, [0x00, 0x01])
+    
+
+    sm_idx = 0
+    genPkt.addBeforeExc(genTcStartFrameCode(gen_file_def, tc_des))
+
+    genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
+                       +genWriteTransPktCode(gen_file_def, sm_idx)
+                       +genTrgTransPktCode(gen_file_def, sm_idx)
+                       +genReadAckPktCode(gen_file_def, sm_idx)
+                      )
+
+
+
+                       #+genTcEndFrameCode(gen_file_def))
+    
+    genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
+    
+    genPkt.clean()
+    genPkt.setPktType(0)
+    
+    #subPkt参数：索引、索引类型、地址、命令、长度、数据
+    genPkt.addSubPkt(0x01, 0, 0x800, 0x1, 768, 
+                     list(range(256)) + list(range(255, -1, -1)) + list(range(256)))
+    
+    
+    
+    gen_file_def_ap01 = gen_file_def + "_rw01"
+    genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap01, 1)
+                       +genWriteTransPktCode(gen_file_def_ap01, 1)
+                       +genTrgTransPktCode(gen_file_def_ap01, 1)
+                      )
+    genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap01)
+    
+    genPkt.clean()
+    genPkt.setPktType(0)
+    
+    #subPkt参数：索引、索引类型、地址、命令、长度、数据
+    genPkt.addSubPkt(0x02, 0, 0x800, 0x1, 256, list(range(128)) + list(range(128)))
+    
+    
+    
+    gen_file_def_ap02 = gen_file_def + "_rw02"
+    sm_idx = 2
+    genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap02, 2)
+                       +genWriteTransPktCode(gen_file_def_ap02, 2)
+                      )
+    genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap02)
+    
+    
+    
+    genPkt.clean()
+    genPkt.setPktType(0)
+    
+    #subPkt参数：索引、索引类型、地址、命令、长度、数据
+    genPkt.addSubPkt(0x03, 0, 0x800, 0x1, 256,  list(range(64)) + list(range(64)) +  list(range(64)) + list(range(64)))
+    
+    
+    
+    gen_file_def_ap03 = gen_file_def + "_rw03"
+    sm_idx = 3
+    genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap03, 3)
+                       +genWriteTransPktCode(gen_file_def_ap03, 3)
+                       +genReadAckPktCode(gen_file_def_ap01, 1)
+                       
+                       +genMessageCode("--读取中断")
+                       +genIFRwDataCode(0, 0x74, False, 4)
+                       +genIFRwDataCode(1, 0x74, False, 4)
+                       +genIFRwDataCode(2, 0x74, False, 4)
+                       +genIFRwDataCode(3, 0x74, False, 4)
+                       +genIFRwDataCode(4, 0x74, False, 4)
+                       
+                       +genMessageCode("--清除中断")
+                       +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       
+                       +genTrgTransPktCode(gen_file_def_ap02, 2)
+                       +genReadAckPktCode(gen_file_def_ap02, 2)
+                       
+                       +genMessageCode("--读取中断")
+                       +genIFRwDataCode(0, 0x74, False, 4)
+                       +genIFRwDataCode(1, 0x74, False, 4)
+                       +genIFRwDataCode(2, 0x74, False, 4)
+                       +genIFRwDataCode(3, 0x74, False, 4)
+                       +genIFRwDataCode(4, 0x74, False, 4)
+                       
+                       +genMessageCode("--清除中断")
+                       +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       
+                       +genTrgTransPktCode(gen_file_def_ap03, 3)
+                       +genReadAckPktCode(gen_file_def_ap03, 3)
+                       
+                       +genMessageCode("--读取中断")
+                       +genIFRwDataCode(0, 0x74, False, 4)
+                       +genIFRwDataCode(1, 0x74, False, 4)
+                       +genIFRwDataCode(2, 0x74, False, 4)
+                       +genIFRwDataCode(3, 0x74, False, 4)
+                       +genIFRwDataCode(4, 0x74, False, 4)
+                       
+                       +genMessageCode("--清除中断")
+                       +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff])
+                       
+                       +genMessageCode("--读取中断")
+                       +genIFRwDataCode(0, 0x74, False, 4)
+                       +genIFRwDataCode(1, 0x74, False, 4)
+                       +genIFRwDataCode(2, 0x74, False, 4)
+                       +genIFRwDataCode(3, 0x74, False, 4)
+                       +genIFRwDataCode(4, 0x74, False, 4)
+                       
+                       
+                       +genIFRwDataCode(1, 0x800, False, 768)
+                       +genIFRwDataCode(2, 0x800, False, 256)
+                       +genIFRwDataCode(3, 0x800, False, 256)
+
+                       +genTcEndFrameCode(gen_file_def)
+                       )
+    genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap03)
+    
+
+    return gen_file_def

tb/shinTest/testcase/environment.py

@@ -161,6 +161,9 @@ def bringup():
                        +genIFRwDataCode(3, 0x400, False, 8)
                        +genIFRwDataCode(4, 0x400, False, 8)
                        
+                       #+genIFRwDataCode(1, 0x0044, True, 4, [0x12, 0x34, 0x56, 0x78])
+                       #+genIFRwDataCode(1, 0x0044, False, 4)
+                       
                        +genTcEndFrameCode(gen_file_def)
                        )
     genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap)

tb/shinTest/testcase/sync.py

@@ -1325,15 +1325,49 @@ def tc7():
                        +genEnableInsertTimeCode(0xa)
         + '''spi_trans( (16'h0100), (`SPI_READ), (8), (`IF_IDX(0)));\n'''
         + '''_temp_time = rxBuf[3] + (rxBuf[4] << 8) + (rxBuf[5] << 16) + (rxBuf[6] << 24) + (rxBuf[7] << 32) + (rxBuf[8] << 40) + (rxBuf[9] << 48) + (rxBuf[10] << 56);\n'''
-        + '''_temp_time = _temp_time + 32'h3000;\n\n''')
+        + '''_temp_time = _temp_time + 32'h3000;\n\n'''
+        + '''txBuf[3] = 8'h0f;\n'''
+        + '''txBuf[4] = 8'h00;\n'''
+        + '''txBuf[5] = 8'h0a;\n'''
+        + '''txBuf[6] = 8'h00;\n'''
+        + '''txBuf[7] = 8'h0a;\n'''
+        + '''txBuf[8] = 8'h00;\n'''
+        + '''txBuf[9] = 8'h0a;\n'''
+        + '''txBuf[10] = 8'h00;\n'''
+        + '''txBuf[19] = (_temp_time & 8'hff);\n'''
+        + '''txBuf[20] = ((_temp_time >> 8) & 8'hff);\n'''
+        + '''txBuf[21] = ((_temp_time >> 16) & 8'hff);\n'''
+        + '''txBuf[22] = ((_temp_time >> 24) & 8'hff);\n'''
+        + '''txBuf[23] = 0;\n'''
+        + '''txBuf[24] = 0;\n'''
+        + '''txBuf[25] = 0;\n'''
+        + '''txBuf[26] = 0;\n'''
+        + '''txBuf[27] = 8'h80;\n'''
+        + '''txBuf[28] = 8'h00;\n'''
+        + '''txBuf[29] = 8'h00;\n'''
+        + '''txBuf[30] = 8'h00;\n'''
+        + '''txBuf[31] = 8'h00;\n'''
+        + '''txBuf[32] = 8'h00;\n'''
+        + '''txBuf[33] = 8'h00;\n'''
+        + '''txBuf[34] = 8'h00;\n'''
+        + '''txBuf[35] = 8'h00;\n'''
+        + '''txBuf[36] = 8'h00;\n'''
+        + '''txBuf[37] = 8'h00;\n'''
+        + '''txBuf[38] = 8'h00;\n'''
+        + '''txBuf[39] = 8'h00;\n'''
+        + '''spi_trans( (16'h0120), (`SPI_WRITE), (40), (`IF_IDX(0)));\n'''
+                        )
     
     genPkt.addSubPkt(0x0, 0, 0x0, 0xc, 12, b'\0'*12)
 
     #subPkt参数：索引、索引类型、地址、命令、长度、数据
     data = [0,] * 100 #bytearray(b"\0" * 100)
     data[0] = 0x0f  #地址0x120
+    data[1] = 0x0
     data[2] = 0xa
+    data[3] = 0x0
     data[4] = 0xa
+    data[5] = 0x0
     data[6] = 0xa
     data[8] = 0xa