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Merge branch 'mp_eb_dev' into feature/dwupEx

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This commit is contained in:
Ruige Lee
2025-08-29 11:12:53 +08:00
parent 9773752cc8 1a01fa9d72
commit 51d29f1dd7
10 changed files with 409 additions and 23 deletions
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28
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -810,10 +810,10 @@ trait InterfaceSync{ this: InterfaceBase =>
}
for( i <- 0 until 4 ){
when( io.lvds.addrw === ("h122".U(16.W) + (2*i).U)){
syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw )
} .elsewhen( io.lvds.addrw === ("h123".U(16.W) + (2*i).U) ){
syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) )
when( addrw === ("h122".U(16.W) + (2*i).U)){
syncWidth(i) := Cat( syncWidth(i)(15,8), dataw )
} .elsewhen( addrw === ("h123".U(16.W) + (2*i).U) ){
syncWidth(i) := Cat( dataw, syncWidth(i)(7,0) )
}
}
@@ -992,13 +992,18 @@ trait InterfaceSync{ this: InterfaceBase =>
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
syncSign(0) := true.B
syncPoint := syncPoint + cReg.syncPeroid
} .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){
syncSign(0) := false.B
} .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){
syncSign(0) := false.B
}
when( cReg.syncPoint <= cReg.recoTimeStamp ){
syncPoint := syncPoint + cReg.syncPeroid
}
for( i <- 1 until 4 ) {
when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点
@@ -1200,12 +1205,17 @@ trait InterfaceSystem{ this: InterfaceBase =>
intStatus(19) := true.B
}
val intHWErr = Seq(
( ~RegNext(io.intHWTrig(0), false.B) & io.intHWTrig(0)),
( ~RegNext(io.intHWTrig(1), false.B) & io.intHWTrig(1))
)
//下行接收硬件错误
when( io.intHWTrig(0) ){
when( intHWErr(0) ){
intStatus(29) := true.B
}
//上行接收硬件错误
when( io.intHWTrig(1) ){
when( intHWErr(1) ){
intStatus(30) := true.B
}
@@ -1241,8 +1251,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
(0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
(0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
isMstRecCRCErr | //override //主站状态下19为上行crc接收错误 //不会同时发生
io.intHWTrig(0) | //下行接收硬件错误
io.intHWTrig(1) //上行接收硬件错误
intHWErr(0) | //下行接收硬件错误
intHWErr(1) //上行接收硬件错误
when( intPulseResetCnt === intPulseWidth ){
intPulse := false.B

16
src/main/scala/backBoard/shin/MasterParser.scala
View File

@@ -114,14 +114,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
io.downOut.bits.tdata := Mux1H(Seq(
( txCnt < txLen ) ->
MuxCase( io.sram_r.datar, Array(
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> io.cReg.timeStamp(7,0),
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === rplCnt0 ),
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.timeStamp(7,0), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === 0.U ),
( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0),
( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8),
( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),