spi 功能测试通过,资源不足

qei 防跳变
This commit is contained in:
RuigeLee
2024-06-27 18:47:46 +08:00
parent eca0931fa3
commit 5090294a12
6 changed files with 454 additions and 44 deletions

View File

@@ -32,7 +32,13 @@ object testModule extends App {
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new Qei })
))
(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/back/", "-E", "verilog" ) ++ args, Seq(
ChiselGeneratorAnnotation(() => { new SpiSlv })
))
// (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
// ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
// ))