ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

spi 功能测试通过，资源不足

Browse Source 
qei 防跳变
This commit is contained in:
RuigeLee
2024-06-27 18:47:46 +08:00
parent eca0931fa3
commit 5090294a12
6 changed files with 454 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/main/scala/backBoard/Qei.scala
View File

@@ -136,21 +136,24 @@ class Qei extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvQ
}
val cntLatch = for( i <- 0 until 2 ) yield { RegEnable(counter(i), ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & io.lvdsSlv.upstream_tx_data_ready ) }
when( statusPage === 0.U ){
upReg(2) := Cat( isSign(0), invDirect(0), mode(0), isSetVal(0), is2Phase(0), isZPhaseEnable(0), isEnable(0) )
upReg(3) := 0.U
upReg(4) := Cat( isSign(1), invDirect(1), mode(1), isSetVal(1), is2Phase(1), isZPhaseEnable(1), isEnable(1) )
upReg(5) := 0.U
upReg(6) := counter(0)(7,0)
upReg(7) := counter(0)(15,8)
upReg(8) := counter(0)(23,16)
upReg(9) := counter(0)(31,24)
upReg(6) := cntLatch(0)(7,0)
upReg(7) := cntLatch(0)(15,8)
upReg(8) := cntLatch(0)(23,16)
upReg(9) := cntLatch(0)(31,24)
upReg(10) := counter(1)(7,0)
upReg(11) := counter(1)(15,8)
upReg(12) := counter(1)(23,16)
upReg(13) := counter(1)(31,24)
upReg(10) := cntLatch(1)(7,0)
upReg(11) := cntLatch(1)(15,8)
upReg(12) := cntLatch(1)(23,16)
upReg(13) := cntLatch(1)(31,24)
}
}