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spi 功能测试通过，资源不足

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qei 防跳变
This commit is contained in:
RuigeLee
2024-06-27 18:47:46 +08:00
parent eca0931fa3
commit 5090294a12
6 changed files with 454 additions and 44 deletions
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19
src/main/scala/backBoard/Qei.scala
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@@ -136,21 +136,24 @@ class Qei extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvQ
}
val cntLatch = for( i <- 0 until 2 ) yield { RegEnable(counter(i), ~RegNext(io.lvdsSlv.upstream_tx_data_ready, false.B) & io.lvdsSlv.upstream_tx_data_ready ) }
when( statusPage === 0.U ){
upReg(2) := Cat( isSign(0), invDirect(0), mode(0), isSetVal(0), is2Phase(0), isZPhaseEnable(0), isEnable(0) )
upReg(3) := 0.U
upReg(4) := Cat( isSign(1), invDirect(1), mode(1), isSetVal(1), is2Phase(1), isZPhaseEnable(1), isEnable(1) )
upReg(5) := 0.U
upReg(6) := counter(0)(7,0)
upReg(7) := counter(0)(15,8)
upReg(8) := counter(0)(23,16)
upReg(9) := counter(0)(31,24)
upReg(6) := cntLatch(0)(7,0)
upReg(7) := cntLatch(0)(15,8)
upReg(8) := cntLatch(0)(23,16)
upReg(9) := cntLatch(0)(31,24)
upReg(10) := counter(1)(7,0)
upReg(11) := counter(1)(15,8)
upReg(12) := counter(1)(23,16)
upReg(13) := counter(1)(31,24)
upReg(10) := cntLatch(1)(7,0)
upReg(11) := cntLatch(1)(15,8)
upReg(12) := cntLatch(1)(23,16)
upReg(13) := cntLatch(1)(31,24)
}
}

113
src/main/scala/backBoard/SpiSlv.scala Normal file
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@@ -0,0 +1,113 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
def page: Int
val sck = Wire(Bool())
val mosi = Wire(Bool())
val csn = Wire(Bool())
val clk100M = Wire(Bool())
val localReg = for( i <- 0 until page ) yield {Reg(Vec(31, UInt(8.W)))}
val localUpdate = RegInit(0.U(16.W))
val shiftSCK = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
val shiftCSn = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
val exReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt((8*31).W)) }
val cmd_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8.W)) }
val pageSel = cmd_100M(7,4)
val spiCmd = cmd_100M(3,0)
val localPage = PriorityMux( ( 0 until page ).map{ i => ( i.U === pageSel ) -> localReg(i) } )
val cnt_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(4.W)) }
// val misoReg = withClockAndReset( clk100M.asClock, reset ){ Reg(Bool()) }
withClockAndReset( clk100M.asClock, reset ){//100M
when( shiftCSn(2) & ~shiftCSn(1) ){
cnt_100M := 0.U
// misoReg := false.B
} .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M < 8.U ){
cmd_100M := Cat( cmd_100M(6,0), shiftMOSI(1) )
cnt_100M := cnt_100M + 1.U
} .elsewhen( isSckNegedge & ~shiftCSn(1) & cnt_100M === 8.U ){
exReg_100M := Mux( spiCmd.extract(1), Cat( localUpdate, 0.U((8*29).W) ), Cat( localPage.reverse) )
cnt_100M := cnt_100M + 1.U
} .elsewhen( isSckPosedge & ~shiftCSn(1) & cnt_100M === 9.U ){
// misoReg := exReg_100M.extract(exReg_100M.getWidth-1)
exReg_100M := Cat( exReg_100M(exReg_100M.getWidth-2 ,0), shiftMOSI(1) )
}
}
}
class SpiSlv extends BackBoardSlvLocal
with BackBoardSlvStatusPR
with BackBoardSpiSlv{
def page: Int = 1
val spi = IO(new Bundle{
val sck = Input(Bool())
val mosi = Input(Bool())
val miso = Output(Bool())
val csn = Input(Bool())
})
val clk100MIO = IO(Input(Bool()))
sck := spi.sck
mosi := spi.mosi
csn := spi.csn
spi.miso := exReg_100M.extract(exReg_100M.getWidth-1)
clk100M := clk100MIO
val shiftCSn_10M = ShiftRegisters(csn, 3, true.B, true.B)
for( i <- 0 until page ){
when( isCrcPass ){
when( downRegTemp(0)(3,0) === i.U ){
localUpdate := localUpdate & ~( 1.U << i )
for( j <- 1 until 32 ) {
localReg(i)(j-1) := downRegTemp(j)
}
}
} .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 1.U ){
when( i.U === pageSel ){
for( j <- 0 until 31 ) {
localReg(i)(30-j) := exReg_100M(8*j+7,8*j)
}
}
} .elsewhen( ~shiftCSn_10M(2) & shiftCSn_10M(1) & spiCmd === 3.U ){
localUpdate := localUpdate & (~exReg_100M(15,0))
}
when( statusPage === i.U ){
for( j <- 1 until 32 ) {
upReg(j) := localReg(i)(j-1)
}
}
}
}

35
src/main/scala/backBoard/SpiSlv.scala.bk
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@@ -1,35 +0,0 @@
package BACK
import chisel3._
import chisel3.util._
trait BackBoardSpiSlv{ this: BackBoardSlvLocal =>
val sck = Wire(Bool())
val mosi = Wire(Bool())
val csn = Wire(Bool())
val clk100M = Wire(Bool())
val shiftSCK = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(sck, 3, false.B, true.B) }
val shiftCSn = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(csn, 3, true.B, true.B) }
val shiftMOSI = withClockAndReset( clk100M.asClock, reset ){ ShiftRegisters(mosi, 3) }
val isSckPosedge = ~shiftSCK(2) & shiftSCK(1)
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1)
val downReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8*8.W)) }
val upReg_100M = withClockAndReset( clk100M.asClock, reset ){ Reg(UInt(8*8.W)) }
val misoReg = withClockAndReset( clk100M.asClock, reset ){ Reg(Bool()) }
withClockAndReset( clk100M.asClock, reset ){//100M
when( isSckPosedge & shiftCSn(2) ){
misoReg := downReg_100M.extract(0)
downReg_100M := downReg_100M >> 1
upReg_100M := Cat( upReg_100M(8*8-1,1), shiftMOSI(2) )
}
}
}