spi 功能测试通过，资源不足

qei 防跳变

Makefile

@@ -19,6 +19,7 @@ back:
 	cp ./src/main/verilog/di16_top.v ./generated/back/
 	cp ./src/main/verilog/do16_top.v ./generated/back/
 	cp ./src/main/verilog/qei_top.v ./generated/back/
+	cp ./src/main/verilog/spi_top.v ./generated/back/
 	cp ./src/main/verilog/defineParam.v ./generated/back/