finish macrx
This commit is contained in:
RuigeLee
@@ -1,6 +1,379 @@
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package MAC
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import chisel3._
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import chisel3.util
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import chisel3.util._
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class MacRxIO extends Bundle{
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val MRxDV = Input(Bool())
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val MRxD = Input(UInt(4.W))
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val Transmitting = Input(Bool())
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val HugEn = Input(Bool())
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val DlyCrcEn = Input(Bool())
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val MaxFL = Input(UInt(16.W))
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val r_IFG = Input(Bool())
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val MAC = Input(UInt(48.W)) // Station Address
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val r_Bro = Input(Bool()) // broadcast disable
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val r_Pro = Input(Bool()) // promiscuous enable
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val r_HASH0 = Input(UInt(32.W)) // lower 4 bytes Hash Table
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val r_HASH1 = Input(UInt(32.W)) // upper 4 bytes Hash Table
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val PassAll = Input(Bool())
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val ControlFrmAddressOK = Input(Bool())
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val RxData = Output(UInt(8.W))
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val RxValid = Output(Bool())
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val RxStartFrm = Output(Bool())
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val RxEndFrm = Output(Bool())
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val ByteCnt = Output(UInt(16.W))
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val ByteCntEq0 = Output(Bool())
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val ByteCntGreat2 = Output(Bool())
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val ByteCntMaxFrame = Output(Bool())
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val CrcError = Output(Bool())
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val StateIdle = Output(Bool())
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val StatePreamble = Output(Bool())
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val StateSFD = Output(Bool())
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val StateData = Output(UInt(2.W))
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val RxAbort = Output(Bool())
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val AddressMiss = Output(Bool())
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}
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abstract class MacRxBase extends Module{
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val io: MacRxIO = IO(new MacRxIO)
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val MRxDEqD = io.MRxD === "hd".U
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val MRxDEq5 = io.MRxD === "h5".U
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val IFGCounterEq24 = Wire(Bool())
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val ByteCntEq0 = Wire(Bool())
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io.ByteCntEq0 := ByteCntEq0
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val ByteCntEq1 = Wire(Bool())
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val ByteCntEq2 = Wire(Bool())
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val ByteCntEq3 = Wire(Bool())
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val ByteCntEq4 = Wire(Bool())
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val ByteCntEq5 = Wire(Bool())
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val ByteCntEq6 = Wire(Bool())
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val ByteCntEq7 = Wire(Bool())
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val ByteCntSmall7 = Wire(Bool())
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val DlyCrcCnt = RegInit(0.U(4.W))
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val StateData0 = RegInit(false.B)
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val StateData1 = RegInit(false.B)
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val StateIdle = RegInit(false.B); io.StateIdle := StateIdle
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val StateDrop = RegInit(true.B)
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val StatePreamble = RegInit(false.B); io.StatePreamble := StatePreamble
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val StateSFD = RegInit(false.B); io.StateSFD := StateSFD
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val RxData_d = RegInit(0.U(8.W))
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val RxData = RegNext(RxData_d, 0.U); io.RxData := RxData
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val Broadcast = RegInit(false.B)
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val Multicast = RegInit(false.B)
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val Crc = RegInit("hFFFFFFFF".U(32.W))
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}
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trait MacRxFSM { this: MacRxBase =>
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val StateData = Cat( StateData1, StateData0 )
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io.StateData := StateData
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// Defining the next state
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val StartIdle = ~io.MRxDV & (StateDrop | StatePreamble | StateSFD | StateData0 | StateData1 )
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val StartPreamble = io.MRxDV & ~MRxDEq5 & (StateIdle & ~io.Transmitting)
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val StartSFD = io.MRxDV & MRxDEq5 & (StateIdle & ~io.Transmitting | StatePreamble)
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val StartData0 = io.MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1)
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val StartData1 = io.MRxDV & StateData0 & (~io.ByteCntMaxFrame)
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val StartDrop = io.MRxDV & (
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(StateIdle & io.Transmitting) | (StateSFD & ~IFGCounterEq24 & MRxDEqD ) | ( StateData0 & io.ByteCntMaxFrame)
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)
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when(StartPreamble | StartSFD | StartDrop){
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StateIdle := false.B
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} .elsewhen( StartIdle ){
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StateIdle := true.B
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}
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when( StartIdle ){
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StateDrop := false.B
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} .elsewhen(StartDrop){
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StateDrop := true.B
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}
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when(StartSFD | StartIdle | StartDrop ){
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StatePreamble := false.B
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} .elsewhen(StartPreamble){
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StatePreamble := true.B
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}
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when(StartPreamble | StartIdle | StartData0 | StartDrop){
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StateSFD := false.B
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} .elsewhen (StartSFD){
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StateSFD := true.B
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}
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when(StartIdle | StartData1 | StartDrop){
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StateData0 := false.B
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} .elsewhen(StartData0){
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StateData0 := true.B
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}
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when(StartIdle | StartData0 | StartDrop){
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StateData1 := false.B
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} .elsewhen(StartData1){
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StateData1 := true.B
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}
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}
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trait MacRxCounter { this: MacRxBase =>
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val ByteCnt = RegInit(0.U(16.W))
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val IFGCounter = RegInit(0.U(5.W))
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val ByteCntMax = ByteCnt === "hffff".U
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val ResetByteCounter = io.MRxDV & (io.StateSFD & MRxDEqD | io.StateData.extract(0) & io.ByteCntMaxFrame)
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val IncrementByteCounter =
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~ResetByteCounter & io.MRxDV & (
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io.StatePreamble | io.StateSFD | io.StateIdle & ~io.Transmitting |
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(io.StateData.extract(1) & ~ByteCntMax & ~(io.DlyCrcEn & DlyCrcCnt.orR))
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)
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val ByteCntDelayed = ByteCnt + 4.U
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io.ByteCnt := Mux(io.DlyCrcEn, ByteCntDelayed, ByteCnt)
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when( DlyCrcCnt === 9.U ){
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DlyCrcCnt := 0.U
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} .elsewhen(io.DlyCrcEn & io.StateSFD){
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DlyCrcCnt := 1.U
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} .elsewhen(io.DlyCrcEn & (DlyCrcCnt.orR)){
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DlyCrcCnt := DlyCrcCnt + 1.U
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}
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when( ResetByteCounter ){
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ByteCnt := 0.U
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} .elsewhen(IncrementByteCounter){
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ByteCnt := ByteCnt + 1.U
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}
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ByteCntEq0 := ByteCnt === 0.U
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ByteCntEq1 := ByteCnt === 1.U
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ByteCntEq2 := ByteCnt === 2.U
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ByteCntEq3 := ByteCnt === 3.U
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ByteCntEq4 := ByteCnt === 4.U
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ByteCntEq5 := ByteCnt === 5.U
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ByteCntEq6 := ByteCnt === 6.U
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ByteCntEq7 := ByteCnt === 7.U
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io.ByteCntGreat2 := ByteCnt > 2.U
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ByteCntSmall7 := ByteCnt < 7.U
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io.ByteCntMaxFrame := (ByteCnt === io.MaxFL) & ~io.HugEn;
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val ResetIFGCounter = io.StateSFD & io.MRxDV & MRxDEqD | StateDrop;
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val IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | io.StateIdle | io.StatePreamble | io.StateSFD) & ~IFGCounterEq24;
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when( ResetIFGCounter ){
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IFGCounter := 0.U
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} .elsewhen(IncrementIFGCounter){
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IFGCounter := IFGCounter + 1.U
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}
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IFGCounterEq24 := (IFGCounter === "h18".U) | io.r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
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}
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trait MacRxFAddrCheck { this: MacRxBase =>
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val HashBit = Wire(UInt(1.W))
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val BroadcastOK = Broadcast & ~io.r_Bro
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val RxCheckEn = io.StateData.orR
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val RxAbort = RegInit(false.B) // Address Error Reported at end of address cycle// RxAbort clears after one cycle
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val AddressMiss = RegInit(false.B) // This ff holds the "Address Miss" information that is written to the RX BD status.
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val MulticastOK = RegInit(false.B) // Hash Address Check, Multicast
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val UnicastOK = RegInit(false.B) // Address Detection (unicast) // start with ByteCntEq2 due to delay of addres from RxData
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io.RxAbort := RxAbort
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io.AddressMiss := AddressMiss
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val RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | io.r_Pro);
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val CrcHash = RegInit(0.U(6.W))
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val CrcHashGood = RegNext(StateData0 & ByteCntEq6) // Latching CRC for use in the hash table
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when(RxAddressInvalid & ByteCntEq7 & RxCheckEn){
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RxAbort := true.B
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} .otherwise{
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RxAbort := false.B
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}
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when(ByteCntEq0){
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AddressMiss := false.B
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} .elsewhen(ByteCntEq7 & RxCheckEn){
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AddressMiss := (~(UnicastOK | BroadcastOK | MulticastOK | (io.PassAll & io.ControlFrmAddressOK)));
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}
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when(io.RxEndFrm | RxAbort){
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MulticastOK := false.B
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} .elsewhen(CrcHashGood & Multicast){
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MulticastOK := HashBit
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}
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when(RxCheckEn & ByteCntEq2){
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UnicastOK := RxData === io.MAC(47,40)
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} .elsewhen(RxCheckEn & ByteCntEq3){
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UnicastOK := ( RxData === io.MAC(39,32)) & UnicastOK
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} .elsewhen(RxCheckEn & ByteCntEq4){
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UnicastOK := ( RxData === io.MAC(31,24)) & UnicastOK
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} .elsewhen(RxCheckEn & ByteCntEq5){
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UnicastOK := ( RxData === io.MAC(23,16)) & UnicastOK
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} .elsewhen(RxCheckEn & ByteCntEq6){
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UnicastOK := ( RxData === io.MAC(15,8)) & UnicastOK
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} .elsewhen(RxCheckEn & ByteCntEq7){
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UnicastOK := ( RxData === io.MAC(7,0)) & UnicastOK
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} .elsewhen(io.RxEndFrm | RxAbort){
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UnicastOK := false.B
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}
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val IntHash = Mux(CrcHash.extract(5), io.r_HASH1, io.r_HASH0)
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val ByteHash =
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Mux1H(Seq(
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(CrcHash(4,3) === "b00".U) -> IntHash(7 ,0),
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(CrcHash(4,3) === "b01".U) -> IntHash(15,8),
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(CrcHash(4,3) === "b10".U) -> IntHash(23,16),
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(CrcHash(4,3) === "b11".U) -> IntHash(31,24),
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))
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HashBit := ByteHash >> CrcHash(2,0)
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when(StateIdle){
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CrcHash := 0.U
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} .elsewhen(StateData0 & ByteCntEq6){
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CrcHash := Crc(31,26)
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}
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}
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trait MacRxCRC { this: MacRxBase =>
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val Data_Crc = Cat(io.MRxD.extract(0),io.MRxD.extract(1),io.MRxD.extract(2),io.MRxD.extract(3))
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val Enable_Crc = io.MRxDV & (io.StateData.orR & ~io.ByteCntMaxFrame)
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val Initialize_Crc = io.StateSFD | (io.DlyCrcEn & DlyCrcCnt > 0.U & DlyCrcCnt < 9.U)
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when( Initialize_Crc ){
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Crc := "hFFFFFFFF".U
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} .otherwise{
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Crc := Cat(
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Crc.extract(27),
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Crc.extract(26),
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(Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(25),
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(Enable_Crc & (Data_Crc.extract(2) ^ Crc.extract(30))) ^ Crc.extract(24),
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(Enable_Crc & (Data_Crc.extract(1) ^ Crc.extract(29))) ^ Crc.extract(23),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(0) ^ Crc.extract(31) ^ Crc.extract(28))) ^ Crc.extract(22),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Crc.extract(31) ^ Crc.extract(30))) ^ Crc.extract(21),
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(Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(30) ^ Crc.extract(29))) ^ Crc.extract(20),
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(Enable_Crc & (Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(29) ^ Crc.extract(28))) ^ Crc.extract(19),
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(Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))) ^ Crc.extract(18),
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Crc.extract(17),
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Crc.extract(16),
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(Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(15),
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(Enable_Crc & (Data_Crc.extract(2) ^ Crc.extract(30))) ^ Crc.extract(14),
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(Enable_Crc & (Data_Crc.extract(1) ^ Crc.extract(29))) ^ Crc.extract(13),
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(Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))) ^ Crc.extract(12),
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(Enable_Crc & (Data_Crc.extract(3) ^ Crc.extract(31))) ^ Crc.extract(11),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(10),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(9),
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(Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract(8),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(7),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(6),
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(Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract(5),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(4),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(3),
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(Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30))) ^ Crc.extract( 2),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(31))) ^ Crc.extract(1),
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(Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(30) ^ Crc.extract(31))) ^ Crc.extract(0),
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Enable_Crc & (Data_Crc.extract(3) ^ Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Crc.extract(29) ^ Crc.extract(30) ^ Crc.extract(31)),
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Enable_Crc & (Data_Crc.extract(2) ^ Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29) ^ Crc.extract(30)),
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Enable_Crc & (Data_Crc.extract(1) ^ Data_Crc.extract(0) ^ Crc.extract(28) ^ Crc.extract(29)),
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Enable_Crc & (Data_Crc.extract(0) ^ Crc.extract(28))
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)
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}
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io.CrcError := Crc =/= "hc704dd7b".U // CRC not equal to magic number
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}
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class MacRx extends MacRxBase with MacRxFSM with MacRxCounter with MacRxFAddrCheck with MacRxCRC{
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val GenerateRxValid = StateData0 & (~ByteCntEq0 | DlyCrcCnt >= 3.U);
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val DelayData = RegNext(StateData0, false.B)
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val LatchedByte = RegInit(0.U(8.W))
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when(true.B) {
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LatchedByte := Cat(io.MRxD, LatchedByte(7,4))// Latched byte
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}
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// Output byte stream
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when( GenerateRxValid ){
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RxData_d := LatchedByte & Fill(8, StateData0 | StateData1) // Data goes through only in data state
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} .elsewhen(~DelayData){
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RxData_d := 0.U // Delaying data to be valid for two cycles. // Zero when not active.
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}
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when(StateData0 & LatchedByte =/= "hFF".U & ByteCntSmall7){
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Broadcast := false.B
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} .elsewhen(StateData0 & LatchedByte === "hFF".U & ByteCntEq1){
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Broadcast := true.B
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} .elsewhen(io.RxAbort | io.RxEndFrm){
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Broadcast := false.B
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}
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when(StateData0 & ByteCntEq1 & LatchedByte.extract(0)){
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Multicast := true.B
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} .elsewhen(io.RxAbort | io.RxEndFrm){
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Multicast := false.B
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}
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io.RxValid := ShiftRegister(GenerateRxValid, 2, false.B, true.B)
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val GenerateRxStartFrm = StateData0 & ( (ByteCntEq1 & ~io.DlyCrcEn) | ((DlyCrcCnt === 3.U) & io.DlyCrcEn) )
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io.RxStartFrm := ShiftRegister(GenerateRxStartFrm, 2, false.B, true.B)
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val GenerateRxEndFrm = StateData0 & ((~io.MRxDV & io.ByteCntGreat2) | io.ByteCntMaxFrame)
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val DribbleRxEndFrm = StateData1 & ~io.MRxDV & io.ByteCntGreat2
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val RxEndFrm_d = RegNext(GenerateRxEndFrm, false.B)
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io.RxEndFrm := RegNext(RxEndFrm_d | DribbleRxEndFrm, false.B)
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}
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@@ -7,7 +7,7 @@ import chisel3.stage._
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object testModule extends App {
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(new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-e", "verilog" ) ++ args, Seq(
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ChiselGeneratorAnnotation(() => {
|
||||
new MIIM()
|
||||
new MacRx()
|
||||
})
|
||||
))
|
||||
}
|
||||
Reference in New Issue
Block a user