check chain

Makefile

@@ -80,16 +80,16 @@ VSimBack:
 	--timescale "1 ns / 1 ps" \
 	-y ${PWD}/tb/ \
 	-y ${PWD}/generated/ \
-	--top-module BackPlaneMstTest \
+	--top-module BackPlaneChainTest \
 	--trace-fst \
-	--cc ./generated/BackPlaneMstTest.v  \
+	--cc ./generated/BackPlaneChainTest.v  \
 	+define+RANDOMIZE_GARBAGE_ASSIGN \
 	+define+RANDOMIZE_INVALID_ASSIGN \
 	+define+RANDOMIZE_REG_INIT \
 	+define+RANDOMIZE_MEM_INIT \
 	+define+RANDOMIZE_DELAY=0 \
 	--exe --build \
-	${PWD}/tb/sim_backMst.cpp \
+	${PWD}/tb/sim_backChain.cpp \
 	-Mdir ./tb/build/ \
 	-j 30
 

src/test/scala/gcd/BackPlaneChainTest.scala

@@ -0,0 +1,87 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+class BackPlaneChainTestIO extends Bundle{
+
+  val clk400 = Input( Vec(6, Bool() ))
+
+
+
+
+  val spi = Flipped(Decoupled(new CDR_Master_Interface_Bundle))
+
+  val led = Output( Vec( 5, Bool() ) )
+
+
+}
+
+class BackPlaneChainTest extends Module{
+  val io: BackPlaneChainTestIO = IO(new BackPlaneChainTestIO)
+
+
+  val mst = Module(new BackBoardMst)
+  val slv = for( i <- 0 until 5 ) yield { Module(new BackBoardSlv) }
+
+
+
+  mst.io.clk4 := io.clk400(5)
+
+
+  withClockAndReset( io.clk400(5).asClock, reset.asAsyncReset ){
+    io.spi.ready := true.B
+    val cnt = RegInit(0.U(7.W))
+    val spiInfo = Reg( new CDR_Master_Interface_Bundle )
+    mst.io.MOSI := spiInfo.asUInt().extract( 6+8+32+2+16-1 )
+    val cs   = RegInit(true.B);  mst.io.CS   := cs
+    val sckCnt = RegInit(1.U(2.W)); mst.io.SCK := sckCnt.extract(1) === 1.U
+
+
+    when( ~cs ){
+      sckCnt := sckCnt + 1.U
+    }
+
+    when( io.spi.fire ){
+      cs := false.B
+      cnt := 0.U
+      spiInfo := io.spi.bits
+    } .elsewhen( cnt =/= 63.U & sckCnt === "b11".U ){
+      cnt := cnt + 1.U
+      spiInfo := Cat(spiInfo.asUInt( 6+8+32+2+16-2, 0 ), mst.io.MISO).asTypeOf(new CDR_Master_Interface_Bundle)
+    } .elsewhen( cnt === 63.U & sckCnt === "b11".U ){
+      cs := true.B
+    }
+  }
+
+
+  for( i <- 0 until 5 ) {
+    slv(i).io.localHost := i.U
+    slv(i).io.clk4 := io.clk400(i)
+
+    slv(i).sw := 0.U
+    slv(i).qeiA := false.B
+    slv(i).qeiB := false.B
+    io.led(i) := slv(i).led.extract(0).asBool
+
+  }
+
+
+  slv(0).io.upStreamReqDat := mst.io.downStreamRespdat
+  mst.io.downStreamReqDat  := slv(0).io.upStreamRespdat
+
+  slv(1).io.upStreamReqDat := slv(0).io.downStreamRespdat
+  slv(0).io.downStreamReqDat  := slv(1).io.upStreamRespdat
+
+  slv(2).io.upStreamReqDat := slv(1).io.downStreamRespdat
+  slv(1).io.downStreamReqDat  := slv(2).io.upStreamRespdat
+
+  slv(3).io.upStreamReqDat := slv(2).io.downStreamRespdat
+  slv(2).io.downStreamReqDat  := slv(3).io.upStreamRespdat
+
+  slv(4).io.upStreamReqDat := slv(3).io.downStreamRespdat
+  slv(3).io.downStreamReqDat  := slv(4).io.upStreamRespdat  
+
+ 
+  slv(4).io.downStreamReqDat := slv(4).io.downStreamRespdat
+}

src/test/scala/gcd/test.scala

@@ -21,7 +21,7 @@ object testModule extends App {
     ))
 
   (new chisel3.stage.ChiselStage).execute( Array("--target-dir", "generated/", "-E", "verilog" ) ++ args, Seq(
-      ChiselGeneratorAnnotation(() => { new BackPlaneMstTest })
+      ChiselGeneratorAnnotation(() => { new BackPlaneChainTest })
     ))
 
   // val cfg = new MacCfg

tb/sim_backChain.cpp

@@ -0,0 +1,244 @@
+/*
+  Copyright (c) 2020 - 2023 Wuhan University of Technology <295054118@whut.edu.cn>
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
+*/
+
+
+#include <verilated.h>
+#include "VBackPlaneChainTest.h"
+#include <memory>
+#include <iostream>
+#include <getopt.h>
+
+#include <sstream>
+
+
+
+#if VM_TRACE
+#include "verilated_fst_c.h"
+#endif
+
+
+char* img;
+VBackPlaneChainTest *top;
+#if VM_TRACE
+VerilatedFstC* tfp;
+#endif
+vluint64_t main_time = 0;
+
+double sc_time_stamp () {
+	return main_time;
+}
+
+
+
+static void sim_exit(){
+#if VM_TRACE
+	tfp->close();
+#endif
+
+	top->final();
+
+	delete top;
+}
+
+
+
+
+
+
+int main(int argc, char **argv, char **env) {
+
+
+	top = new VBackPlaneChainTest();
+
+#if VM_TRACE
+	tfp = new VerilatedFstC;
+    Verilated::traceEverOn(true);
+    top->trace(tfp, 99); // Trace 99 levels of hierarchy
+    tfp->open("./tb/build/wave.fst");		
+#endif
+
+
+
+
+
+	top->reset = 1;
+	top->clock = 0;
+    top->io_clk400_0 = 0;
+    top->io_clk400_1 = 0;
+    top->io_clk400_2 = 0;
+    top->io_clk400_3 = 0;
+    top->io_clk400_4 = 0;
+    top->io_clk400_5 = 0;
+	
+	while(!Verilated::gotFinish()) {
+
+		Verilated::timeInc(1);
+
+		if ( main_time != 1000 ){
+		} else {
+			top->reset = 0;
+		}
+
+		if ( main_time % 400 == 100 ) {
+			top->clock = 1;
+		} else if ( main_time % 400 == 300 ) {
+			top->clock = 0;
+		} 
+
+
+
+
+
+		if ( main_time % 100 == 10 ) {
+			top->io_clk400_0 = 1;
+		} else if ( main_time % 100 == 60 ) {
+			top->io_clk400_0 = 0;
+		}
+
+		if ( main_time % 100 == 20 ) {
+			top->io_clk400_1 = 1;
+		} else if ( main_time % 100 == 70 ) {
+			top->io_clk400_1 = 0;
+		}  
+
+		if ( main_time % 100 == 40 ) {
+			top->io_clk400_2 = 1;
+		} else if ( main_time % 100 == 90 ) {
+			top->io_clk400_2 = 0;
+		}
+
+		if ( main_time % 100 == 5 ) {
+			top->io_clk400_3 = 1;
+		} else if ( main_time % 100 == 55 ) {
+			top->io_clk400_3 = 0;
+		}   
+
+		if ( main_time % 100 == 0 ) {
+			top->io_clk400_4 = 1;
+		} else if ( main_time % 100 == 50 ) {
+			top->io_clk400_4 = 0;
+		} 
+
+		if ( main_time % 100 == 30 ) {
+			top->io_clk400_5 = 1;
+		} else if ( main_time % 100 == 80 ) {
+			top->io_clk400_5 = 0;
+		} 
+
+
+
+        if( main_time == 50000 ){
+            top->io_spi_valid = 1;
+            top->io_spi_bits_address =  0x00 << 1 | 0x01;
+            top->io_spi_bits_register = 0x1;
+            top->io_spi_bits_data = 0xa5;
+            top->io_spi_bits_op = 0x01;
+            top->io_spi_bits_hash = 0x0;
+
+        } else if( main_time == 50100 ){
+            top->io_spi_valid = 0;
+        }
+
+     
+        if( main_time == 250000 ){
+            top->io_spi_valid = 1;
+            top->io_spi_bits_address =  0x01 << 1 | 0x01;
+            top->io_spi_bits_register = 0x1;
+            top->io_spi_bits_data = 0x55;
+            top->io_spi_bits_op = 0x00;
+            top->io_spi_bits_hash = 0x0;
+
+        } else if( main_time == 250100 ){
+            top->io_spi_valid = 0;
+        }
+
+        if( main_time == 450000 ){
+            top->io_spi_valid = 1;
+            top->io_spi_bits_address =  0x02 << 1 | 0x01;
+            top->io_spi_bits_register = 0x1;
+            top->io_spi_bits_data = 0x55;
+            top->io_spi_bits_op = 0x00;
+            top->io_spi_bits_hash = 0x0;
+
+        } else if( main_time == 450100 ){
+            top->io_spi_valid = 0;
+        }
+
+        if( main_time == 650000 ){
+            top->io_spi_valid = 1;
+            top->io_spi_bits_address =  0x03 << 1 | 0x01;
+            top->io_spi_bits_register = 0x1;
+            top->io_spi_bits_data = 0x55;
+            top->io_spi_bits_op = 0x00;
+            top->io_spi_bits_hash = 0x0;
+
+        } else if( main_time == 650100 ){
+            top->io_spi_valid = 0;
+        }
+
+        if( main_time == 850000 ){
+            top->io_spi_valid = 1;
+            top->io_spi_bits_address =  0x04 << 1 | 0x01;
+            top->io_spi_bits_register = 0x1;
+            top->io_spi_bits_data = 0x55;
+            top->io_spi_bits_op = 0x00;
+            top->io_spi_bits_hash = 0x0;
+
+        } else if( main_time == 850100 ){
+            top->io_spi_valid = 0;
+        }
+
+        if( main_time == 1050000 ){
+            top->io_spi_valid = 1;
+            top->io_spi_bits_address =  0x05 << 1 | 0x01;
+            top->io_spi_bits_register = 0x1;
+            top->io_spi_bits_data = 0x55;
+            top->io_spi_bits_op = 0x00;
+            top->io_spi_bits_hash = 0x0;
+
+        } else if( main_time == 1050100 ){
+            top->io_spi_valid = 0;
+        }
+
+
+
+		top->eval();
+#if VM_TRACE
+		tfp->dump(Verilated::time());			
+
+#endif
+
+
+		main_time ++;
+
+        if( main_time > 3050000 ){
+            break;
+        }
+	}
+	
+	sim_exit();
+	return -1;
+
+
+}
+
+
+
+
+
+
+
+