临时切换

2025-04-27 14:56:07 +08:00
parent 7b63b07408
commit 4f8ee9466c
3 changed files with 216 additions and 101 deletions
--- a/src/main/scala/backBoard/shin/MasterParser.scala
+++ b/src/main/scala/backBoard/shin/MasterParser.scala
@@ -1,100 +1,122 @@
-// package BACK
+package BACK

-// import chisel3._
-// import chisel3.util._
+import chisel3._
+import chisel3.util._

-// class MasterParserIO extends Module{
-//   val downOut = Decoupled(new AXIS_Bundle(8))
-//   val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
+class MasterParserIO extends Module{
+  val downOut = Decoupled(new AXIS_Bundle(8))
+  val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )

-//   val sram_r = Flipped(new ShareSRAMIO)
-//   val sram_w = Flipped(new ShareSRAMIO)
+  val sram_r = Flipped(new ShareSRAMIO)
+  val sram_w = Flipped(new ShareSRAMIO)

-//   val req = Valid(new Bundle{
-//     val length  = UInt(12.W)
-//   })
-//   val rsp = Valid(new Bundle{
-//     val isError = Bool()
-//     val length  = UInt(12.W)
-//   })
+  val req = Valid(new Bundle{
+    val txAddr    = UInt(15.W)
+    val rxAddr    = UInt(15.W)
+    val length  = UInt(12.W)
+  })
+  val rsp = Valid(new Bundle{
+    val isError = Bool()
+    val length  = UInt(12.W)
+  })

+  val rxEnq = Output( Bool())
+  val txDeq  = Output( Bool())

+  val trigAddr = Input( Vec(2, UInt(15.W)) )

-// }
+  val timeStamp = Input(UInt(64.W))

-// abstract class MasterParserBase extends Module{
-//   val io: MasterParserIO = IO(new MasterParserIO)
+}

-//   val sendCnt = Reg(UInt(11.W))
-//   val sendLen = Reg(UInt(11.W))
+abstract class MasterParserBase extends Module{
+  val io: MasterParserIO = IO(new MasterParserIO)

-//   val reqReady = RegInit(true.B)
-//   val sendAddr = Reg(UInt(12.W))
+  val sendCnt = Reg(UInt(11.W))
+  val sendLen = Reg(UInt(11.W))
+  val txAddr = Reg(UInt(15.W))

-//   io.req.ready := reqReady
+  val rxCnt = Reg(UInt(11.W))
+  val rxAddr = Reg(UInt(15.W))

-//   when( io.req.fire ){
-//     reqReady := false.B
-//   } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
-//     reqReady := true.B
-//   }
+  val reqReady = RegInit(true.B)
+  val sendAddr = Reg(UInt(12.W))

-//   when( io.req.fire ){
-//     sendLen := io.req.bits.length
-//     sendCnt := 0.U
-//   } .elsewhen( io.downOut.fire ){
-//     sendCnt := sendCnt + 1.U
-//   }
+  io.req.ready := reqReady

-//   when( reqReady ){
-//     sendAddr := 0.U
-//   } .elsewhen( io.downOut.fire ){
-//     sendAddr := sendAddr + 1.U
-//   }
+  when( io.req.fire ){
+    reqReady := false.B
+  } .elsewhen( io.downOut.fire & sendCnt === sendLen ){
+    reqReady := true.B
+  }

-//   io.sram_r.enr := 
-//     io.req.fire | io.downOut.fire
+  when( io.req.fire ){
+    sendLen  := io.req.bits.length
+    sendCnt  := 0.U
+  } .elsewhen( io.downOut.fire ){
+    sendCnt := sendCnt + 1.U
+  }

-//   io.sram_r.addr := Mux( io.req.fire, io.req.bits.addr, sendCnt )
+  when( io.req.fire ){
+    txAddr := io.req.bits.txAddr
+  } .elsewhen( io.downOut.fire ){
+    txAddr := txAddr + 1.U
+  }

-//   io.downOut.valid := ~reqReady
-//   io.downOut.bits.tdata := io.req.bits.datar
-//   io.downOut.bits.tuser := false.B 
-//   io.downOut.bits.tlast := sendCnt === sendLen
+  when( io.req.fire ){
+    rxAddr := io.req.bits.rxAddr
+  } .elsewhen( io.upIn.fire ){
+    rxAddr := rxAddr + 1.U
+  }

+  when( reqReady ){
+    sendAddr := 0.U
+  } .elsewhen( io.downOut.fire ){
+    sendAddr := sendAddr + 1.U
+  }

+  io.sram_r.enr := 
+    io.req.fire | io.downOut.fire

+  io.sram_r.addr := Mux( io.req.fire, io.req.bits.txAddr, txAddr + 1.U )

-//   val recAddr = Reg(UInt(12.W))
-
-//   io.upIn.ready := true.B
-
-//   io.sram_w.enw := io.upIn.fire
-//   io.sram_w.addr := recAddr
-//   io.sram_w.dataw := io.upIn.bits.tdata
-
-
-//   when( io.upIn.fire ){
-//     when( io.upIn.bits.tlast ){
-//       recAddr := 0.U
-//     } .otherwise{
-//       recAddr := recAddr + 1.U
-//     }
-//   }
-
-//   io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
-//   io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
-//   io.rsp.bits.length  := recAddr
+  io.downOut.valid := ~reqReady
+  io.downOut.bits.tdata := io.sram_r.datar
+  io.downOut.bits.tuser := false.B 
+  io.downOut.bits.tlast := sendCnt === sendLen





+  when( io.req.fire ){
+    rxCnt := 0.U
+  } .elsewhen( io.upIn.fire ){
+    rxCnt := rxCnt + 1.U
+  }


-// }
+  io.upIn.ready := true.B
+
+  io.sram_w.enw := io.upIn.fire
+  io.sram_w.addr := rxAddr
+  io.sram_w.dataw := io.upIn.bits.tdata


-// class MasterParser extends MasterParserBase{
+  io.rsp.valid := io.upIn.fire & io.upIn.bits.tlast
+  io.rsp.bits.isError := io.upIn.fire & io.upIn.bits.tuser
+  io.rsp.bits.length  := rxCnt + 1.U

-// }
+
+
+  io.rxEnq := io.trigAddr(0) === txCnt         & io.downOut.fire
+  io.txDeq := io.trigAddr(1) === (rxCnt + 1.U) & io.upIn.fire
+
+
+
+}
+
+
+class MasterParser extends MasterParserBase{
+
+}
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -32,18 +32,19 @@ class ShinTopIO extends Bundle{
  val sram_r = Vec( 4, new SRAM2kRDIO) //QSPI


+  val modeSel = Input(Bool())
 }



-class ShinTop extends Module{
+abstract class ShinTopBase extends Module{
  val io: ShinTopIO = IO(new ShinTopIO)

  // val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
 	// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }

 	val slaveParser  = Module(new SlaveParser )
-	// val masterParser = Module(new MasterParser)
+	val masterParser = Module(new MasterParser)


  val smUnit = Seq(
@@ -69,20 +70,14 @@ class ShinTop extends Module{
  )


-  smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
-  smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
-  smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
-  smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
+

  smUnit(0).io.sram_r <> io.sram_r(0)
  smUnit(2).io.sram_r <> io.sram_r(1)
  smUnit(4).io.sram_r <> io.sram_r(2)
  smUnit(6).io.sram_r <> io.sram_r(3)

-  smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
-  smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
-  smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
-  smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
+

  smUnit(1).io.sram_w := io.sram_w(0)
  smUnit(3).io.sram_w := io.sram_w(1)
@@ -90,11 +85,6 @@ class ShinTop extends Module{
  smUnit(7).io.sram_w := io.sram_w(3)


-  smUnit(0).io.enq := slaveParser.io.dSMenq(0)
-  smUnit(2).io.enq := slaveParser.io.dSMenq(1)
-  smUnit(4).io.enq := slaveParser.io.dSMenq(2)
-  smUnit(6).io.enq := slaveParser.io.dSMenq(3)
-
  smUnit(0).io.deq := io.dSMdeq(0)
  smUnit(2).io.deq := io.dSMdeq(1)
  smUnit(4).io.deq := io.dSMdeq(2)
@@ -106,12 +96,30 @@ class ShinTop extends Module{
  smUnit(5).io.enq := io.uSMenq(2)
  smUnit(7).io.enq := io.uSMenq(3)

-  smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
-  smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
-  smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
-  smUnit(7).io.deq := slaveParser.io.uSMdeq(3)


+  when( io.modeSel === false.B ){
+    smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
+    smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
+    smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
+    smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
+
+    smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
+    smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
+    smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
+    smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
+
+    smUnit(0).io.enq := slaveParser.io.dSMenq(0)
+    smUnit(2).io.enq := slaveParser.io.dSMenq(1)
+    smUnit(4).io.enq := slaveParser.io.dSMenq(2)
+    smUnit(6).io.enq := slaveParser.io.dSMenq(3)
+
+    smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
+    smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
+    smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
+    smUnit(7).io.deq := slaveParser.io.uSMdeq(3)    
+  }
+



@@ -145,11 +153,70 @@ class ShinTop extends Module{



+  when(io.modeSel === false.B ){
+    slaveParser.io.downIn  <> io.downIn
+    slaveParser.io.downOut <> io.downOut
+    slaveParser.io.upIn    <> io.upIn
+    slaveParser.io.upOut   <> io.upOut    
+  }

-  slaveParser.io.downIn  <> io.downIn
-  slaveParser.io.downOut <> io.downOut
-  slaveParser.io.upIn    <> io.upIn
-  slaveParser.io.upOut   <> io.upOut
+
+
+
+
+
+
+
+
+}
+
+
+trait ShinTopMaster{ this: ShinTopBase =>
+    val downOut = Decoupled(new AXIS_Bundle(8))
+    val upIn  = Flipped( Decoupled(new AXIS_Bundle(8)) )
+
+
+  when( io.modeSel === true.B ){
+    smUnit(0).io.sram_w := masterParser.io.sram_w(0)
+    smUnit(1).io.sram_r <> masterParser.io.sram_r(0)
+
+
+    smUnit(0).io.enq := slaveParser.io.rxEnq
+    smUnit(1).io.deq := slaveParser.io.txDeq
+
+  }
+    val sram_r = Flipped(new ShareSRAMIO)
+    val sram_w = Flipped(new ShareSRAMIO)
+
+    val req = Valid(new Bundle{
+      val txAddr    = UInt(15.W)
+      val rxAddr    = UInt(15.W)
+      val length  = UInt(12.W)
+    })
+    val rsp = Valid(new Bundle{
+      val isError = Bool()
+      val length  = UInt(12.W)
+    })
+
+    val txDeq = Output( Bool())
+    val rx Enq  = Output( Bool())
+
+  masterParser.io.trigAddr(0) := "hff".U
+  masterParser.io.trigAddr(1) := "hff".U
+
+  masterParser.io.timeStamp := io.timeStamp
+}
+
+
+trait ShinTopSlave{ this: ShinTopBase =>
+
+
+  when( io.modeSel === false.B ){
+    slaveParser.io.downIn  <> io.downIn
+    slaveParser.io.downOut <> io.downOut
+    slaveParser.io.upIn    <> io.upIn
+    slaveParser.io.upOut   <> io.upOut
+  }

  slaveParser.io.timeStamp := io.timeStamp

@@ -167,4 +234,39 @@ class ShinTop extends Module{



+  when( io.modeSel === false.B ){
+    smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
+    smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
+    smUnit(4).io.sram_w := slaveParser.io.sram_w(2)
+    smUnit(6).io.sram_w := slaveParser.io.sram_w(3)
+
+    smUnit(1).io.sram_r <> slaveParser.io.sram_r(0)
+    smUnit(3).io.sram_r <> slaveParser.io.sram_r(1)
+    smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
+    smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
+
+    smUnit(0).io.enq := slaveParser.io.dSMenq(0)
+    smUnit(2).io.enq := slaveParser.io.dSMenq(1)
+    smUnit(4).io.enq := slaveParser.io.dSMenq(2)
+    smUnit(6).io.enq := slaveParser.io.dSMenq(3)
+
+    smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
+    smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
+    smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
+    smUnit(7).io.deq := slaveParser.io.uSMdeq(3)    
+  }
+
+
+
+
+
 }
+
+
+
+
+
+
+class ShinTop extends ShinTopBase
+with ShinTopMaster
+with ShinTopSlave
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -117,12 +117,6 @@ abstract class SlaveParserBase extends Module{
  }


-
-
-  // val isDownSendProbe: Bool //下行探针
-  // val isUpSendProbe: Bool   //上行探针
-  // val probeFrame: FrameHeader //固定化探针内容
-
  downSendGen.io.frameReq.valid :=
    isDownSendPend & downRecParser.io.subMsgReq.fire //| 下行转发
    //isDownSendProbe  //下行探针
@@ -367,9 +361,6 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
 trait SlaveParserRW{ this: SlaveParserBase =>


-
-
-
  //下行接收
  when( downRecParser.io.subMsgReq.fire ){
    when( isDownRecPing ){