修复sync的64位加法器输入位宽转换问题

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -818,6 +818,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   val addr64_res = addr64_op1 + addr64_op2
 
   val addrConflict = WireDefault(VecInit(Seq.fill(4){false.B}))
+  dontTouch(addrConflict)
   assert( PopCount(addrConflict) <= 1.U )
 
 
@@ -933,8 +934,8 @@ trait SlaveParserSync{ this: SlaveParserBase =>
   when( RegNext(isSync) & ~isSync ){
     // deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
 
-    addr64_op1 := mstDeltaTimeStamp //组合逻辑
-    addr64_op2 := subOp2(slvDeltaTimeStamp) //组合逻辑
+    addr64_op1 := Cat( Fill(32, mstDeltaTimeStamp(31)), mstDeltaTimeStamp) //组合逻辑
+    addr64_op2 := subOp2( Cat( Fill(32, slvDeltaTimeStamp(31)), slvDeltaTimeStamp) ) //组合逻辑
     addrConflict(2) := true.B //组合逻辑
     deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1))  //时序逻辑