主站的ctrlWord

doc/spec/物理层优化.md

@@ -41,6 +41,9 @@
 * CDR_IN的控制字由补充状态机STATE_CTRL过滤后输出
 * PRE SDF的控制字在包末尾将允许重复使用
 
+* 主站寄存器增加"h600"指向CDR_OUT的ctrlWord
+
+
 ---------------------------------------
 
 以下是大模型补充区域

src/main/scala/backBoard/shin/Interface.scala

@@ -114,6 +114,8 @@ class MasterRegisterBundle extends Bundle{
   val isRecCRCErr  = UInt(4.W)
   val rplTimeStampTx = UInt(16.W)
   val timeStampOffset = UInt(64.W)
+
+  val ctrlWord = UInt(8.W)
 }
 
 
@@ -519,6 +521,9 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
       ( 0 until 8 ).map{ i =>
         ( addr === ("h540".U(16.W) + i.U) )  -> cReg.event.lvdsSMTimeStampDeq( 8*i+7, 8*i+0 )
       } ++
+      Seq(
+        (addr === "h600".U(16.W)) -> mReg.ctrlWord,
+      ) ++
       Seq()
 
     )
@@ -623,6 +628,8 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   mReg.txSM     := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )
 
+  mReg.ctrlWord := RegEnable( dataw(7,0), "h1c".U(8.W), isEnW & addrw === "h600".U )
+
   val mReg_isRecCRCErr = RegInit(0.U(4.W))
   mReg.isRecCRCErr := mReg_isRecCRCErr
   when( isEnW & addrw === "h22".U(16.W) ){

src/main/scala/backBoard/shin/MstSlvSwitch.scala

@@ -75,6 +75,9 @@ abstract class MstSlvSwitchBase extends Module with RequireAsyncReset{
   interface.io.intTransEnd(2) := upCDRInAxis.io.axis.fire    & upCDRInAxis.io.axis.bits.tlast
   interface.io.intTransEnd(3) := upCDROut.io.axis.fire   & upCDROut.io.axis.bits.tlast
   
+  downCDROut.io.ctrlWord := interface.io.mReg.ctrlWord
+  upCDROut.io.ctrlWord   := interface.io.mReg.ctrlWord
+
   io.isSoftReset := interface.io.isSoftReset
   io.interrupt   := interface.io.interrupt