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This commit is contained in:
Ruige Lee
2025-08-28 15:51:17 +08:00
parent 9bb59c350a
commit 4b88e4937d
3 changed files with 55 additions and 33 deletions
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80
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -59,7 +59,9 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val isSpiRead = spiCmd === 1.U
val bitSel = Reg(UInt(3.W))
val bitSelNext = RegNext(bitSel)
val byteSel = Reg(UInt(12.W))
val byteSelNext = RegNext(byteSel)
@@ -95,17 +97,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrr := exRegi
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi)
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrr := addrr + 1.U
}
}
@@ -116,16 +108,17 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
class SSpiInterface extends SpiInterfaceBase{
val spi = IO(new SSPIInterfaceIO)
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
sck := spi.sck
csn := spi.csn
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & spi.miso === 1.U & byteSel === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === 1.U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := spi.miso
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(1)
}
@@ -137,23 +130,23 @@ class SSpiInterface extends SpiInterfaceBase{
bitSel := bitSel + 1.U
}
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftMOSI(1) )
}.otherwise{
exRegi := Cat( exRegi(6 ,0), shiftMOSI(1) )
exRegi := Cat( exRegi(6,0), shiftMOSI(1) )
}
}
//输出在SCK下降沿准备数据
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckNegedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){
when((byteSel === 1.U || byteSel === 2.U) ){
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
when( bitSel.andR ){
when((byteSel === 0.U || byteSel === 1.U) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
exRego := io.datar
@@ -162,10 +155,26 @@ class SSpiInterface extends SpiInterfaceBase{
exRego := exRego << 1
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrr := Cat( exRegi(6,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI(1))
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 2.U & bitSelNext === 0.U ){
addrr := addrr + 1.U
}
}
}
class QSpiInterface extends SpiInterfaceBase{
val qspi = IO(new QSPIInterfaceIO)
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
sck := qspi.sck
csn := qspi.csn
@@ -173,11 +182,11 @@ class QSpiInterface extends SpiInterfaceBase{
qspi.isDirIn := ~isSpiRead
io.isEnR :=
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & qspi.miso === "b1000".U & byteSel === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U)
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & shiftMOSI(1) === "b1000".U & byteSelNext === 2.U ) |
(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSelNext === 0.U & isSpiRead & byteSelNext >= 3.U)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSel === 2.U & bitSel === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := qspi.miso.extract(3)
when( isSckPosedgeNext(0) & ~shiftCSn(1) & byteSelNext === 2.U & bitSelNext === 0.U ){ //CS为低，且SCK上跳的第0byte
spiCmd := shiftMOSI(1).extract(3)
}
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -186,7 +195,7 @@ class QSpiInterface extends SpiInterfaceBase{
bitSel := ~bitSel
}
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
@@ -195,16 +204,16 @@ class QSpiInterface extends SpiInterfaceBase{
when( bitSel === 0.U ){
exRegi := Cat( 0.U, shiftMOSI(1) )
}.otherwise{
exRegi := Cat( exRegi(3 ,0), shiftMOSI(1) )
exRegi := Cat( exRegi(3,0), shiftMOSI(1) )
}
}
//输出在SCK下降沿准备数据
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
exRego := 0.U //第一个byte 地址0
} .elsewhen( isSckNegedge & ~shiftCSn(1) ){
when( bitSel === 0.U ){
when((byteSel === 1.U || byteSel === 2.U) ){
} .elsewhen( isSckPosedge & ~shiftCSn(1) ){
when( bitSel.andR ){
when((byteSel === 0.U || byteSel === 1.U) ){
exRego := 0.U //地址1，cmd
} .elsewhen( isSpiRead ){
exRego := io.datar
@@ -214,6 +223,19 @@ class QSpiInterface extends SpiInterfaceBase{
}
}
when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳
addrr := 0.U
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 0.U){ //CS为低，且SCK上跳的第0byte
addrr := Cat( exRegi(3,0), shiftMOSI(1) )
} .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(addrr(7,0), exRegi(3,0), shiftMOSI(1))
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(0) & byteSelNext >= 2.U & bitSelNext === 0.U ){
addrr := addrr + 1.U
}
}
}