diff --git a/tb/shinTest/shinSim/easybusSim.py b/tb/shinTest/shinSim/easybusSim.py index 4e431ab..5baf873 100644 --- a/tb/shinTest/shinSim/easybusSim.py +++ b/tb/shinTest/shinSim/easybusSim.py @@ -1,5 +1,11 @@ import array + +HOST_WRITE = 0 +HOST_READ = 1 +LVDS_WRITE = 2 +LVDS_READ = 3 + class ArrayUintRef: """对 array 某个元素的引用代理""" def __init__(self, arr, index, t = 0): @@ -286,17 +292,18 @@ class device(object): l = len(data) ret = False for k, v in enumerate(range(addr, addr+l)): - ret = (self.__ctrl_regs_hw(v, data[k]) - or self.__reset_ctrl_regs_hw(v, data[k]) - or self.__int_regs_hw(v, data[k]) - or self.__stat_regs_hw(v, data[k]) - or self.__link_regs_hw(v, data[k]) - or self.__sync_regs_hw(v, data[k]) - or self.__custom_def_regs_hw(v, data[k]) - or self.__ebmmu_regs_hw(v, data[k]) - or self.__sm_regs_hw(v, data[k]) - or self.__watch_dog_regs_hw(v, data[k]) - or self.__event_regs_hw(v, data[k]) + ret = (self.__ctrl_regs_wr(HOST_WRITE, v, data[k]) + or self.__trans_ctrl_regs_wr(HOST_WRITE, v, data[k]) + or self.__reset_ctrl_regs_wr(HOST_WRITE, v, data[k]) + or self.__int_regs_wr(HOST_WRITE, v, data[k]) + or self.__stat_regs_wr(HOST_WRITE, v, data[k]) + or self.__link_regs_wr(HOST_WRITE, v, data[k]) + or self.__sync_regs_wr(HOST_WRITE, v, data[k]) + or self.__custom_def_regs_wr(HOST_WRITE, v, data[k]) + or self.__ebmmu_regs_wr(HOST_WRITE, v, data[k]) + or self.__sm_regs_wr(HOST_WRITE, v, data[k]) + or self.__watch_dog_regs_wr(HOST_WRITE, v, data[k]) + or self.__event_regs_wr(HOST_WRITE, v, data[k]) ) # self.__init_temp_regs() @@ -319,79 +326,204 @@ class device(object): pass - def __ctrl_regs_hw(self, regaddr, val): + def __ctrl_regs_wr(self, op, regaddr, val, *args): + if 0x0 <= regaddr <= 0x19: + pass + else: + return False + if regaddr == 0x00: - self.reg[regaddr] = val & 0xff - + if op == HOST_WRITE: + self.reg[regaddr] = val & 0xff + elif op == LVDS_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif regaddr == 0x01: # 硬件版本号，写入无效 - pass - + if (op == HOST_WRITE) or (op == LVDS_WRITE): + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0x02 <= regaddr <= 0x07: # 硬件编码，写入无效 - pass + if (op == HOST_WRITE) or (op == LVDS_WRITE): + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif regaddr == 0x09: #硬件接口(0,1,2,3,4,5) - self.reg[regaddr] = val & 0xff - + if op == HOST_WRITE: + self.reg[regaddr] = val & 0xff + elif op == LVDS_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass + + elif 0xa <= regaddr <= 0xb: + #EasyBus站点地址 + if (op == HOST_READ) or (op == LVDS_READ): + if self.role.value == 2: + val[args[0]] = self.reg[regaddr] + else: + pass + elif 0x10 <= regaddr <= 0x17: #硬件唯一编码，写入无效 - pass + if (op == HOST_WRITE) or (op == LVDS_WRITE): + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0x18 <= regaddr <= 0x19: #lvds写入锁 - if self.role.value == 1: + if (op == HOST_WRITE) or (op == LVDS_WRITE): + if self.role.value == 1: + pass + elif self.role.value == 2: + if regaddr == 0x18: + self.lvds_0x18 = val & 0x1 + elif regaddr == 0x19: + if val == 0x58: + self.reg[regaddr] = self.lvds_0x18 + else: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass + + else: + return False + + return True + + def __trans_ctrl_regs_wr(self, op, regaddr, val, *args): + if 0x20 <= regaddr <= 0x25: + pass + else: + return False + + if (self.role.value >= 2) or (self.role.value < 1): + return True + + if regaddr == 0x20: + if op == HOST_WRITE: + self.reg[regaddr] = val & 0xff + en_tx = (val & 0x1) + buf_no = (val >> 1) & 0x3 + #buf_rx = (val >> 3) & 0x3 + if en_tx == 0x1: + self.reg[regaddr] = self.reg[regaddr] & 0xfe + #发送数据 + pass + elif op == LVDS_WRITE: + pass + elif (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + elif (op == LVDS_READ): + #val[args[0]] = 0 + pass + else: + pass + + elif 0x22 <= regaddr <= 0x23: + if op == HOST_WRITE: + self.reg[0x22] = 0 + self.reg[0x23] = 0 + elif op == LVDS_WRITE: + pass + elif (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + elif (op == LVDS_READ): + pass + else: + pass + + elif 0x24 <= regaddr <= 0x25: + if op == HOST_WRITE: + self.reg[regaddr] = val & 0xff + elif op == LVDS_WRITE: + pass + elif (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + elif (op == LVDS_READ): pass - elif self.role.value == 2: - if regaddr == 0x18: - self.lvds_0x18 = val & 0x1 - elif regaddr == 0x19: - if val == 0x58: - self.reg[regaddr] = self.lvds_0x18 else: pass else: return False return True - - def __reset_ctrl_regs_hw(self, regaddr, val): + + def __reset_ctrl_regs_wr(self, op, regaddr, val, *args): + if 0x40 <= regaddr <= 0x55: + pass + else: + return False + #EasyBus复位 if 0x40 <= regaddr <= 0x43: - if regaddr == 0x40: - self.reset_0x40 = val & 0x1 - elif regaddr == 0x41: - self.reset_0x41 = 0 - elif regaddr == 0x42: - self.reset_0x42 = val & 0xff - elif regaddr == 0x43: - self.reset_0x43 = val & 0xff + if (op == LVDS_WRITE) and (op == LVDS_READ): + pass + + elif op == HOST_WRITE: + if regaddr == 0x40: + self.reset_0x40 = val & 0x1 + elif regaddr == 0x41: + self.reset_0x41 = 0 + elif regaddr == 0x42: + self.reset_0x42 = val & 0xff + elif regaddr == 0x43: + self.reset_0x43 = val & 0xff + else: + pass + + if (self.reset_0x42 == 0x66) and (self.reset_0x43 == 0x79): + if self.reset_0x40 == 0x1: + #重启芯片 + self.reset_0x42 = 0 + self.reset_0x43 = 0 + #self.reset_0x40 = 0 + #self.reset_0x41 = 0 + else: + pass + elif op == HOST_READ: + val[args[0]] = self.reg[regaddr] else: pass - if (self.reset_0x42 == 0x66) and (self.reset_0x43 == 0x79): - if self.reset_0x40 == 0x1: - #重启芯片 - self.reset_0x42 = 0 - self.reset_0x43 = 0 - #self.reset_0x40 = 0 - #self.reset_0x41 = 0 - else: - pass - #交换上下行管脚 elif 0x4a <= regaddr <= 0x4b: - if regaddr == 0x4a: - self.swap_dir_0x4a = val & 0xff - elif regaddr == 0x4b: - self.swap_dir_0x4b = val & 0xff - if self.swap_dir_0x4b == 0x58: - self.reg[0x4a] = self.swap_dir_0x4a - self.swap_dir_0x4b = 0x0 - #进行管脚交换 + if (op == LVDS_WRITE) and (op == LVDS_READ): + pass + + elif op == HOST_WRITE: + if regaddr == 0x4a: + self.swap_dir_0x4a = val & 0xff + elif regaddr == 0x4b: + self.swap_dir_0x4b = val & 0xff + if self.swap_dir_0x4b == 0x58: + self.reg[0x4a] = self.swap_dir_0x4a + self.swap_dir_0x4b = 0x0 + #进行管脚交换 + else: + pass else: pass + elif op == HOST_READ: + val[args[0]] = self.reg[regaddr] else: pass @@ -400,148 +532,328 @@ class device(object): #BIT15-BIT8:key，当KEY = 0x59，且BIT0为1时，4b5b；BIT0为0时，8b10b。 #读取时KEY始终为0。KEY不正确，不响应修改 elif 0x4c <= regaddr <= 0x4d: - if regaddr == 0x4c: - self.code_sel_0x4c = val & 0xff - elif regaddr == 0x4d: - self.code_sel_0x4d = val & 0xff - if self.code_sel_0x4d == 0x59: - self.reg[0x4c] = self.code_sel_0x4c - self.code_sel_0x4d = 0 - #切换编码 + if (op == LVDS_WRITE) and (op == LVDS_READ): + pass + + elif op == HOST_WRITE: + if regaddr == 0x4c: + self.code_sel_0x4c = val & 0xff + elif regaddr == 0x4d: + self.code_sel_0x4d = val & 0xff + if self.code_sel_0x4d == 0x59: + self.reg[0x4c] = self.code_sel_0x4c + self.code_sel_0x4d = 0 + #切换编码 + else: + pass else: pass + elif op == HOST_READ: + val[args[0]] = self.reg[regaddr] else: pass #CDR参数 elif 0x4e <= regaddr <= 0x4f: - if regaddr == 0x4e: - self.cdr_type_0x4e = val & 0xff - elif regaddr == 0x4f: - self.cdr_type_0x4f = val & 0xff - if self.cdr_type_0x4f == 0x60: - self.reg[0x4e] = self.cdr_type_0x4e - self.cdr_type_0x4f = 0x0 - #执行cdr参数 + if (op == LVDS_WRITE) and (op == LVDS_READ): + pass + + elif op == HOST_WRITE: + if regaddr == 0x4e: + self.cdr_type_0x4e = val & 0xff + elif regaddr == 0x4f: + self.cdr_type_0x4f = val & 0xff + if self.cdr_type_0x4f == 0x60: + self.reg[0x4e] = self.cdr_type_0x4e + self.cdr_type_0x4f = 0x0 + #执行cdr参数 + else: + pass else: pass + elif op == HOST_READ: + val[args[0]] = self.reg[regaddr] else: pass #4倍频分频系数 elif regaddr == 0x55: - pass + if (op == LVDS_WRITE) and (op == LVDS_READ): + pass + + elif op == HOST_WRITE: + pass + + elif op == HOST_READ: + val[args[0]] = self.reg[regaddr] + else: + pass + else: return False return True - def __int_regs_hw(self, regaddr, val): + def __int_regs_wr(self, op, regaddr, val, *args): + if 0x70 <= regaddr <= 0x7d: + pass + else: + return False + #中断使能 if 0x70 <= regaddr <= 0x73: - self.reg[regaddr] = val & 0xff - self.reg[0x73] = self.reg[0x73] | 0x80 + if (op == LVDS_WRITE): + pass + elif op == HOST_WRITE: + self.reg[regaddr] = val & 0xff + self.reg[0x73] = self.reg[0x73] | 0x80 + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass #中断状态 elif 0x74 <= regaddr <= 0x77: #只读 #warning - pass + if (op == LVDS_WRITE) or (op == HOST_WRITE): + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass #中断状态清除 elif 0x78 <= regaddr <= 0x7b: - self.reg[regaddr - 0x4] = (~val) & self.reg[regaddr - 0x4] - self.int_status[regaddr - 0x78] = (~val) & self.int_status[regaddr - 0x78] + if (op == LVDS_WRITE): + pass + elif op == HOST_WRITE: + self.reg[regaddr - 0x4] = (~val) & self.reg[regaddr - 0x4] + self.int_status[regaddr - 0x78] = (~val) & self.int_status[regaddr - 0x78] + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass #中断模式 elif 0x7c <= regaddr <= 0x7d: - self.reg[regaddr] = val & 0xff + if (op == LVDS_WRITE): + pass + elif op == HOST_WRITE: + self.reg[regaddr] = val & 0xff + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass else: return False return True - def __stat_regs_hw(self, regaddr, val): + def __stat_regs_wr(self, op, regaddr, val, *args): #统计 #下行接收错误计数器（包括包不完全、CDR、CRC、超时） if 0x80 <= regaddr <= 0x81: - regaddr[0x80] = 0 - regaddr[0x81] = 0 + if (op == LVDS_WRITE): + regaddr[0x80] = 0 + regaddr[0x81] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass + elif 0x82 <= regaddr <= 0x83: - regaddr[0x82] = 0 - regaddr[0x83] = 0 + if (op == LVDS_WRITE): + regaddr[0x82] = 0 + regaddr[0x83] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0x84 <= regaddr <= 0x85: - regaddr[0x84] = 0 - regaddr[0x85] = 0 + if (op == LVDS_WRITE): + regaddr[0x84] = 0 + regaddr[0x85] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0x86 <= regaddr <= 0x87: - regaddr[0x86] = 0 - regaddr[0x87] = 0 + if (op == LVDS_WRITE): + regaddr[0x86] = 0 + regaddr[0x87] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0x88 <= regaddr <= 0x89: - regaddr[0x88] = 0 - regaddr[0x89] = 0 + if (op == LVDS_WRITE): + regaddr[0x88] = 0 + regaddr[0x89] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0x8a <= regaddr <= 0x8b: - regaddr[0x8a] = 0 - regaddr[0x8b] = 0 + if (op == LVDS_WRITE): + regaddr[0x8a] = 0 + regaddr[0x8b] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0x8c <= regaddr <= 0x8f: - regaddr[0x8c] = 0 - regaddr[0x8f] = 0 + if (op == LVDS_WRITE): + regaddr[0x8c] = 0 + regaddr[0x8f] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0x90 <= regaddr <= 0x97: - regaddr[0x90] = 0 - regaddr[0x91] = 0 - regaddr[0x92] = 0 - regaddr[0x93] = 0 - regaddr[0x94] = 0 - regaddr[0x95] = 0 - regaddr[0x96] = 0 - regaddr[0x97] = 0 + if (op == LVDS_WRITE): + regaddr[0x90] = 0 + regaddr[0x91] = 0 + regaddr[0x92] = 0 + regaddr[0x93] = 0 + regaddr[0x94] = 0 + regaddr[0x95] = 0 + regaddr[0x96] = 0 + regaddr[0x97] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass #上行 elif 0xa0 <= regaddr <= 0xa1: - regaddr[0xa0] = 0 - regaddr[0xa1] = 0 + if (op == LVDS_WRITE): + regaddr[0xa0] = 0 + regaddr[0xa1] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0xa2 <= regaddr <= 0xa3: - regaddr[0xa2] = 0 - regaddr[0xa3] = 0 + if (op == LVDS_WRITE): + regaddr[0xa2] = 0 + regaddr[0xa3] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0xa4 <= regaddr <= 0xa5: - regaddr[0xa4] = 0 - regaddr[0xa5] = 0 + if (op == LVDS_WRITE): + regaddr[0xa4] = 0 + regaddr[0xa5] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0xa6 <= regaddr <= 0xa7: - regaddr[0xa6] = 0 - regaddr[0xa7] = 0 + if (op == LVDS_WRITE): + regaddr[0xa6] = 0 + regaddr[0xa7] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0xa8 <= regaddr <= 0xa9: - regaddr[0xa8] = 0 - regaddr[0xa9] = 0 + if (op == LVDS_WRITE): + regaddr[0xa8] = 0 + regaddr[0xa9] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0xaa <= regaddr <= 0xab: - regaddr[0xaa] = 0 - regaddr[0xab] = 0 + if (op == LVDS_WRITE): + regaddr[0xaa] = 0 + regaddr[0xab] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0xac <= regaddr <= 0xaf: - regaddr[0xac] = 0 - regaddr[0xad] = 0 + if (op == LVDS_WRITE): + regaddr[0xac] = 0 + regaddr[0xad] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif 0xb0 <= regaddr <= 0xb7: - regaddr[0xb0] = 0 - regaddr[0xb1] = 0 - regaddr[0xb2] = 0 - regaddr[0xb3] = 0 - regaddr[0xb4] = 0 - regaddr[0xb5] = 0 - regaddr[0xb6] = 0 - regaddr[0xb7] = 0 + if (op == LVDS_WRITE): + regaddr[0xb0] = 0 + regaddr[0xb1] = 0 + regaddr[0xb2] = 0 + regaddr[0xb3] = 0 + regaddr[0xb4] = 0 + regaddr[0xb5] = 0 + regaddr[0xb6] = 0 + regaddr[0xb7] = 0 + elif op == HOST_WRITE: + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass else: return False return True - def __link_regs_hw(self, regaddr, val): + def __link_regs_wr(self, op, regaddr, val, *args): #两个寄存器都是只读 #链路状态 if 0xc0 <= regaddr <= 0xc1: - pass + if (op == LVDS_WRITE) or (op == HOST_WRITE): + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass #右侧设备地址 elif 0xc2 <= regaddr <= 0xc3: - pass + if (op == LVDS_WRITE) or (op == HOST_WRITE): + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass else: return False @@ -549,9 +861,10 @@ class device(object): return True - def __sync_regs_hw(self, regaddr, val): + def __sync_regs_wr(self, op, regaddr, val, *args): #同步 #这里注意一个问题，主站是否要考虑lvds侧锁不锁的问题 + ''' if 0x0100 <= regaddr <= 0x107: pass elif 0x0108 <= regaddr <= 0x10f: @@ -562,76 +875,158 @@ class device(object): pass elif 0x0118 <= regaddr <= 0x11f: pass - - elif 0x0120 <= regaddr <= 0x121: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - elif 0x0122 <= regaddr <= 0x123: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - elif 0x0124 <= regaddr <= 0x125: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - elif 0x0126 <= regaddr <= 0x127: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - elif 0x0128 <= regaddr <= 0x129: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - - elif 0x0130 <= regaddr <= 0x137: - if (self.reg[0x18] & 0x1) == 0x1: + ''' + if 0x0100 <= regaddr <= 0x11f: + if (op == LVDS_WRITE) or (op == HOST_WRITE): + pass + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass + + ''' + elif 0x0120 <= regaddr <= 0x121: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif 0x0122 <= regaddr <= 0x123: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif 0x0124 <= regaddr <= 0x125: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif 0x0126 <= regaddr <= 0x127: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif 0x0128 <= regaddr <= 0x129: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + ''' + elif 0x0120 <= regaddr <= 0x129: + if (op == LVDS_WRITE): + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif (op == HOST_WRITE): self.reg[regaddr] = val & 0xff + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass - elif 0x0138 <= regaddr <= 0x13b: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - elif 0x013c <= regaddr <= 0x13f: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - elif 0x0140 <= regaddr <= 0x143: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - elif 0x0144 <= regaddr <= 0x147: - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff - - elif 0x0148 <= regaddr <= 0x14f: - if (self.reg[0x18] & 0x1) == 0x1: + + ''' + elif 0x0130 <= regaddr <= 0x137: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + + elif 0x0138 <= regaddr <= 0x13b: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif 0x013c <= regaddr <= 0x13f: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif 0x0140 <= regaddr <= 0x143: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif 0x0144 <= regaddr <= 0x147: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + + elif 0x0148 <= regaddr <= 0x14f: + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + ''' + elif 0x0130 <= regaddr <= 0x14f: + if (op == LVDS_WRITE): + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif (op == HOST_WRITE): self.reg[regaddr] = val & 0xff + elif (op == HOST_READ) or (op == LVDS_READ): + val[args[0]] = self.reg[regaddr] + else: + pass + else: return False return True - def __custom_def_regs_hw(self, regaddr, val): + def __custom_def_regs_wr(self, op, regaddr, val, *args): if 0x180 <= regaddr <= 0x1FF: - self.reg[regaddr] = val & 0xff + if self.role.value == 2: + if (op == LVDS_WRITE) or (op == HOST_WRITE): + self.reg[regaddr] = val & 0xff + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass + else: + pass else: return False return True - def __ebmmu_regs_hw(self, regaddr, val): + def __ebmmu_regs_wr(self, op, regaddr, val, *args): ebmmu_base = 0x200 ebmmu_no = 16 for i in range(ebmmu_no): if (ebmmu_base + i * 0xa) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x3): - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff + if self.role.value == 2: + if (op == LVDS_WRITE): + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif (op == HOST_WRITE): + pass + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif ((ebmmu_base + i * 0xa) + 0x4) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x5): - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff + if self.role.value == 2: + if (op == LVDS_WRITE): + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif (op == HOST_WRITE): + pass + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif ((ebmmu_base + i * 0xa) + 0x6) <= regaddr <= ((ebmmu_base + i * 0xa) + 0x7): - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff + if self.role.value == 2: + if (op == LVDS_WRITE): + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif (op == HOST_WRITE): + pass + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif regaddr == ((ebmmu_base + i * 0xa) + 0x8): - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff + if self.role.value == 2: + if (op == LVDS_WRITE): + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif (op == HOST_WRITE): + pass + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif regaddr == ((ebmmu_base + i * 0xa) + 0x9): - if (self.reg[0x18] & 0x1) == 0x1: - self.reg[regaddr] = val & 0xff + if self.role.value == 2: + if (op == LVDS_WRITE): + if (self.reg[0x18] & 0x1) == 0x1: + self.reg[regaddr] = val & 0xff + elif (op == HOST_WRITE): + pass + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass else: continue @@ -639,7 +1034,7 @@ class device(object): return False - def __sm_regs_hw(self, regaddr, val): + def __sm_regs_wr(self, op, regaddr, val, *args): #数据缓冲区描述寄存器组 ''' self.sm[f'mem{i}'] = MemroyQueueMgr(syncMemNum[i]) @@ -649,32 +1044,81 @@ class device(object): ''' for i in range(8): if regaddr == (0x300 + i * 0x4): - self.sm[f'mem{i}_ctrl'].value = 0 - #复位 - self.sm[f'mem{i}'].reset() - self.sm[f'mem{i}_item_num'].value = 0 + if (op == LVDS_WRITE): + pass + elif (op == HOST_WRITE): + self.sm[f'mem{i}_ctrl'].value = 0 + #复位 + self.sm[f'mem{i}'].reset() + self.sm[f'mem{i}_item_num'].value = 0 + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif regaddr == (0x301 + i * 0x4): - pass + if (op == LVDS_WRITE): + pass + elif (op == HOST_WRITE): + pass + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass elif (0x302 + i * 0x4) <= regaddr <= (0x303 + i * 0x4): - if self.sm[f'mem{i}_item_num'].value == 0: - self.reg[regaddr] = val & 0xff + if (op == LVDS_WRITE) or (op == HOST_WRITE): + if self.sm[f'mem{i}_item_num'].value == 0: + self.reg[regaddr] = val & 0xff + elif (op == LVDS_READ) or (op == HOST_READ): + val[args[0]] = self.reg[regaddr] + else: + pass else: continue return True for i in range(8): - if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800): - self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800] = val - if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value: - self.sm[f'mem{i}'].enq_data() - self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}']) - return True + if self.role.value == 1: + if ((op == LVDS_WRITE)) or ((op == HOST_WRITE)): + if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800): + self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800] = val + if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value: + self.sm[f'mem{i}'].enq_data() + self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}']) + return True + elif ((op == LVDS_READ)) or ((op == HOST_READ)): + if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800): + val[args[0]] = self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800] + if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value: + self.sm[f'mem{i}'].free_data() + self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}']) + return True + else: + pass + elif self.role.value == 2: + if ((op == LVDS_WRITE)) or ((op == HOST_WRITE)): + if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800): + self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800] = val + if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value: + self.sm[f'mem{i}'].enq_data() + self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}']) + return True + elif ((op == LVDS_READ)) or ((op == HOST_READ)): + if (0x800 + i * 0x800) <= regaddr < (0x1000 + i * 0x800): + val[args[0]] = self.sm[f'mem{i}'][regaddr - 0x800 - i * 0x800] + if (regaddr - 0x800 - i * 0x800 + 1) == self.sm[f'mem{i}_len'].value: + self.sm[f'mem{i}'].free_data() + self.sm[f'mem{i}_item_num'].value = len(self.sm[f'mem{i}']) + return True + else: + pass + else: + pass return False - def __watch_dog_regs_hw(self, regaddr, val): + def __watch_dog_regs_wr(self, op, regaddr, val): #看门狗 if 0x400 <= regaddr <= 0x403: pass @@ -725,7 +1169,7 @@ class device(object): return True - def __event_regs_hw(self, regaddr, val): + def __event_regs_wr(self, op, regaddr, val): if 0x500 <= regaddr <= 0x501: pass elif 0x502 <= regaddr <= 0x503: @@ -768,6 +1212,29 @@ if __name__ == '__main__': d1.connect_next(d2) d2.connect_next(d3) + m.hostwrite(0, [1, ]) + d0.hostwrite(0, [2, ]) + d1.hostwrite(0, [2, ]) + d2.hostwrite(0, [2, ]) + d3.hostwrite(0, [2, ]) + + data = m.hostread(0, 128) + print(data) + data = d0.hostread(0, 128) + print(data) + + ''' + m = device() + d0 = device() + d1 = device() + d2 = device() + d3 = device() + + m.connect_next(d0) + d0.connect_next(d1) + d1.connect_next(d2) + d2.connect_next(d3) + m.hostwrite(0, [2,]) data = m.hostread(0, 128) #print(data) @@ -828,3 +1295,27 @@ if __name__ == '__main__': sm0.free_data() print(sm0[:4], len(sm0)) + + def testfunc(op): + if op == 0: + return False, 1, 2, 3 + else: + return True, 3, 2, 1 + + def testfunc2(op, val, *args): + if isinstance(val, list): + val[args[0]] = op + return True + + + a = testfunc(0) + b = testfunc(1) + print(a) + print(b) + + arr = [1, 2, 3] + + print(arr) + testfunc2(100, arr, 0) + print(arr) + '''