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修复接线错误

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This commit is contained in:
RuigeLee
2025-09-06 23:02:10 +08:00
parent 0b0a42afb0
commit 4a21e4b2ba
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/backBoard/shin/MstSlvSwitch.scala
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@@ -635,7 +635,7 @@ trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
when(cdrSelB){ when(cdrSelB){
io.downCDRSampleIn(1).serDat := downInSerDat io.downCDRSampleIn(1).serDat := downInSerDat
io.upCDRSampleIn(1).serDat := downInSerDat io.upCDRSampleIn(1).serDat := upInSerDat
downInSyncSerDat := io.downCDRSampleIn(1).syncSerDat downInSyncSerDat := io.downCDRSampleIn(1).syncSerDat
upInSyncSerDat := io.upCDRSampleIn(1).syncSerDat upInSyncSerDat := io.upCDRSampleIn(1).syncSerDat
@@ -645,7 +645,7 @@ trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
io.upCDRSampleIn(2).serDat := false.B io.upCDRSampleIn(2).serDat := false.B
} .elsewhen(cdrSelC){ } .elsewhen(cdrSelC){
io.downCDRSampleIn(2).serDat := downInSerDat io.downCDRSampleIn(2).serDat := downInSerDat
io.upCDRSampleIn(2).serDat := downInSerDat io.upCDRSampleIn(2).serDat := upInSerDat
downInSyncSerDat := io.downCDRSampleIn(2).syncSerDat downInSyncSerDat := io.downCDRSampleIn(2).syncSerDat
upInSyncSerDat := io.upCDRSampleIn(2).syncSerDat upInSyncSerDat := io.upCDRSampleIn(2).syncSerDat
@@ -655,7 +655,7 @@ trait MstSlvSwitchCDRIn{ this: MstSlvSwitchBase =>
io.upCDRSampleIn(1).serDat := false.B io.upCDRSampleIn(1).serDat := false.B
} .otherwise{ } .otherwise{
io.downCDRSampleIn(0).serDat := downInSerDat io.downCDRSampleIn(0).serDat := downInSerDat
io.upCDRSampleIn(0).serDat := downInSerDat io.upCDRSampleIn(0).serDat := upInSerDat
downInSyncSerDat := io.downCDRSampleIn(0).syncSerDat downInSyncSerDat := io.downCDRSampleIn(0).syncSerDat
upInSyncSerDat := io.upCDRSampleIn(0).syncSerDat upInSyncSerDat := io.upCDRSampleIn(0).syncSerDat