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删除发送错误标志，主站软件改C代码

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This commit is contained in:
RuigeLee
2024-11-04 16:07:06 +08:00
parent 9fa54072f4
commit 4a219df882
6 changed files with 208 additions and 35 deletions
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9
Makefile
View File

@@ -67,11 +67,16 @@ sw:
-c ./tb/sw/src/mstStartup.S \
-o ./tb/sw/build/mstStartup.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
riscv64-unknown-elf-gcc -O3 -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs \
-I ./tb/sw/ -I ./tb/sw/src \
-c ./tb/sw/src/mstMain.S \
-c ./tb/sw/src/mstMain.c \
-o ./tb/sw/build/mstMain.o
# riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -mcmodel=medany -mexplicit-relocs \
# -I ./tb/sw/ -I ./tb/sw/src \
# -c ./tb/sw/src/mstMain.S \
# -o ./tb/sw/build/mstMain.o
riscv64-unknown-elf-gcc -Os -ggdb -march=rv32i -mabi=ilp32 -Wall -mcmodel=medany -mexplicit-relocs -nostdlib -nodefaultlibs -nostartfiles \
-T ./tb/sw/linker.lds \
./tb/sw/build/mstStartup.o \

19
src/main/scala/backBoard/pico/TLCDR.scala
View File

@@ -51,9 +51,9 @@ trait TLCDRTx{ this: TLCDRBase =>
val txLen = RegInit(0.U(12.W))
val isTxBusy = RegInit(false.B)
val isTxFull = ~txFifo.io.enq.ready
val isTxError = RegInit(false.B)
val intTxError = ~RegNext(isTxError, false.B) & isTxError
val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B)
val intTxFifoFull = ~RegNext(isTxFull, false.B) & isTxFull
val intTxFinish = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast
@@ -86,7 +86,7 @@ trait TLCDRTx{ this: TLCDRBase =>
// ))
CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
CDROut.io.axis.bits.tuser := isTxError
CDROut.io.axis.bits.tuser := false.B
CDROut.io.axis.valid := isTxBusy
@@ -115,15 +115,6 @@ trait TLCDRTx{ this: TLCDRBase =>
txFifo.io.enq.bits := io.mem.wdata
txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U
when( isTLWriteTxLen ){
isTxError := false.B
} .elsewhen( isTxFull & isTLWriteTxFifo ){
isTxError := true.B
} .elsewhen( txLen === 0.U & isTLWriteTxFifo ){
isTxError := true.B
}
}
@@ -226,7 +217,7 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
io.interrupt(0) := intTxError
io.interrupt(0) := intTxEnd
io.interrupt(1) := intRxError
io.interrupt(2) := intRxStart
io.interrupt(3) := intRxEnd
@@ -234,7 +225,7 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
io.mem.rdata :=
Mux1H(Seq(
isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError),
isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B),
isTLReadRxLen -> rxLen,
isTLReadRxFifo -> rxFifo.io.deq.bits
))

132
tb/sw/src/MstMain.c Normal file
View File

@@ -0,0 +1,132 @@
#include <stdint.h>
// #include "uart.h"
// #include "gpio.h"
// #include "timer.h"
volatile uint32_t *cdr_status = (uint32_t*)( 0x000 + 0x0 ); //read
volatile uint32_t *cdr_txLen = (uint32_t*)( 0x000 + 0x4 ); //write
volatile uint32_t *cdr_txFifo = (uint32_t*)( 0x000 + 0x8 ); //write
volatile uint32_t *cdr_direct = (uint32_t*)( 0x000 + 0xc ); //write
volatile uint32_t *cdr_softReset = (uint32_t*)( 0x000 + 0x10 ); //write
volatile uint32_t *cdr_rxLen = (uint32_t*)( 0x000 + 0x18 ); //read
volatile uint32_t *cdr_rxFifo = (uint32_t*)( 0x000 + 0x1c ); //read
volatile uint32_t *WriteGpio = (uint32_t*) ( 0x400);
volatile uint32_t *ReadGpio = (uint32_t*) ( 0x400);
volatile uint32_t *ReadIsLast = (uint32_t*) ( 0x408);
static inline void error() {
while(1);
}
void main()
{
uint32_t readDat;
uint32_t operator;
uint32_t downRecvLen;
uint32_t upRecvLen;
uint32_t slvNum;
uint32_t totNum;
uint32_t isLast;
while(1){
*cdr_softReset = 1; //复位脉冲
*cdr_direct = 0;
//发送下行包头
*cdr_txLen = 520; //总长520
*cdr_txFifo = (512 << 20) |( 0 << 16) | 0; //负载长度512，操作数0， 参数全0
*cdr_txFifo = 0;
for( uint32_t i = 0; i < 512/4; i ++ ){
*cdr_txFifo = i;
}
//等待发送完成标志
asm volatile (
"1:\n"
"andi ra, sp, 0x01\n"
"beqz ra, 1b\n"
"andi sp, sp, 0xFE\n"
);
*cdr_softReset = 1; //复位脉冲
*cdr_direct = 1; //方向切换上行
//接收第一个包
asm volatile (
"1:\n"
"andi ra, sp, 0x04\n"
"beqz ra, 1b\n"
"andi sp, sp, 0xFB\n"
);
readDat = *cdr_rxFifo;
// operator = (readDat >> 16) & 0xf; //速度不够，不校验
upRecvLen = readDat >> 20;
//接收第二个包
// asm volatile (
// "andi ra, sp, 0x08\n"
// "1:\n"
// "bnez ra, 1b\n" //error //速度不够，不校验
// );
uint32_t temp = *cdr_rxFifo;
//上行转发负载
for( uint32_t i = 0; i < (upRecvLen >> 2); i ++ ){ //一次传4byte
asm volatile (
"andi ra, sp, 0x80\n"
"1:\n"
"bnez ra, 1b\n" //error 速度不够，不再检查接收
"lw t1, 0x01c(x0)\n"
);
}
//CRC
asm volatile (
"andi ra, sp, 0x08\n"
"1:\n"
"bnez ra, 1b\n" //error
);
uint32_t crc = *cdr_rxFifo; //CRC
//等待接收完成标志
asm volatile (
"1:\n"
"andi ra, sp, 0x08\n"
"beqz ra, 1b\n"
"andi sp, sp, 0xF7\n"
);
totNum = (upRecvLen >> 3);
while(1);
}
}

59
tb/sw/src/SlvMain.c
View File

@@ -126,6 +126,15 @@ void main()
);
if(!isLast){
//等待发送完成标志
asm volatile (
"1:\n"
"andi ra, sp, 0x01\n"
"beqz ra, 1b\n"
"andi sp, sp, 0xFE\n"
);
}
@@ -154,29 +163,41 @@ void main()
);
readDat = *cdr_rxFifo;
operator = (readDat >> 16) & 0xf;
upRecvLen = readDat >> 20;
totNum = slvNum + (upRecvLen >> 3) - 1;
//接收第二个包
asm volatile (
"andi ra, sp, 0x08\n"
"1:\n"
"bnez ra, 1b\n" //error
);
readDat = *cdr_rxFifo;
// operator = (readDat >> 16) & 0xf; //速度不够，不校验
upRecvLen = readDat >> 20;
//发送上行包头
*cdr_txLen = upRecvLen + 16; //upSendLen + 8
*cdr_txFifo = ((upRecvLen + 8) << 20) |( 0 << 16) | 0;
*cdr_txFifo = 0;
for( uint8_t i = 0; i < 8/4; i ++ ){
for( uint32_t i = 0; i < 8/4; i ++ ){
*cdr_txFifo = 0;
}
//接收第二个包
// asm volatile (
// "andi ra, sp, 0x08\n"
// "1:\n"
// "bnez ra, 1b\n" //error //速度不够，不校验
// );
uint32_t temp = *cdr_rxFifo;
//上行转发负载
for( uint16_t i = 0; i < upRecvLen >> 2; i ++ ){ //一次传4byte
for( uint32_t i = 0; i < (upRecvLen >> 2); i ++ ){ //一次传4byte
asm volatile (
"andi ra, sp, 0x80\n"
"1:\n"
@@ -204,19 +225,27 @@ void main()
"andi sp, sp, 0xF7\n"
);
totNum = slvNum + (upRecvLen >> 3) - 1;
} else { //islast
//发送上行包头
*cdr_txLen = 16; //upSendLen + 8
*cdr_txFifo = (8 << 20) |( 0 << 16) | 0;
*cdr_txFifo = 0;
for( uint8_t i = 0; i < 8/4; i ++ ){
for( uint32_t i = 0; i < 8/4; i ++ ){
*cdr_txFifo = 0;
}
}
//等待发送完成标志
asm volatile (
"1:\n"
"andi ra, sp, 0x01\n"
"beqz ra, 1b\n"
"andi sp, sp, 0xFE\n"
);

15
tb/sw/src/mstMain.S
View File

@@ -14,6 +14,8 @@
main:
sw x0, 0x010(x0) # 软复位，写入任意值，0也可以
sw x0, 0x00c(x0) # 配置方向，下行
li x6, 520
sw x6, 0x004(x0) #cdr_0_tx_txLen
@@ -30,7 +32,20 @@ main:
addi x6, x6, -1 # 递减计数器
bnez x6, 1b # 如果计数器不为0，则继续循环
2:
andi ra, sp, 0x01 # 等待发送完成标志位
beqz ra, 2b
andi sp, sp, 0xFE
sw x0, 0x010(x0) # 软复位，写入任意值，0也可以
li x6, 1
sw x6, 0x00c(x0) # 配置方向，上行
3:
j 2b

1
tb/sw/src/mstStartup.S
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@@ -47,6 +47,7 @@ trap_entry:
# q寄存器已经禁用， Without the q-registers, the irq return address will be stored in x3 (gp) and the IRQ bitmask in x4 (tp),
# addi x15, x4, 0
or sp, sp, x4
picorv32_retirq_insn()