删除发送错误标志，主站软件改C代码

src/main/scala/backBoard/pico/TLCDR.scala

@@ -51,9 +51,9 @@ trait TLCDRTx{ this: TLCDRBase =>
   val txLen     = RegInit(0.U(12.W))
   val isTxBusy  = RegInit(false.B)
   val isTxFull  = ~txFifo.io.enq.ready
-  val isTxError = RegInit(false.B)
 
-  val intTxError    = ~RegNext(isTxError, false.B) & isTxError
+
+  val intTxEnd      = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B)
   val intTxFifoFull = ~RegNext(isTxFull, false.B)  & isTxFull
   val intTxFinish   = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast
 
@@ -86,7 +86,7 @@ trait TLCDRTx{ this: TLCDRBase =>
   // ))
 
   CDROut.io.axis.bits.tlast := ~txFifo.io.deq.valid & txCnt === 3.U
-  CDROut.io.axis.bits.tuser := isTxError
+  CDROut.io.axis.bits.tuser := false.B
   CDROut.io.axis.valid := isTxBusy
 
 
@@ -115,15 +115,6 @@ trait TLCDRTx{ this: TLCDRBase =>
   txFifo.io.enq.bits  := io.mem.wdata
   txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U
 
-  when( isTLWriteTxLen ){
-    isTxError := false.B
-  } .elsewhen( isTxFull & isTLWriteTxFifo ){
-    isTxError := true.B
-  } .elsewhen( txLen === 0.U & isTLWriteTxFifo ){
-    isTxError := true.B
-  }
-
-
 
 }
 
@@ -226,7 +217,7 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
 
 
 
-  io.interrupt(0) := intTxError
+  io.interrupt(0) := intTxEnd
   io.interrupt(1) := intRxError
   io.interrupt(2) := intRxStart
   io.interrupt(3) := intRxEnd
@@ -234,7 +225,7 @@ class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCD
 
   io.mem.rdata :=
     Mux1H(Seq(
-      isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError),
+      isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, false.B),
       isTLReadRxLen  -> rxLen,
       isTLReadRxFifo -> rxFifo.io.deq.bits
     ))