SM模块，即用4空位fifo控制的2KB fifo

2025-04-16 16:50:36 +08:00
parent 9cd2e7732b
commit 4962e217dd
2 changed files with 179 additions and 2 deletions
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -79,8 +79,8 @@ abstract class SlaveParserBase extends Module{

  val upFrameInfo  = Reg(new FrameHeader) //上行大包头

-  val isDownSendBusy = downSendGen.io.frameReq.ready
-  val isUpSendBusy   =   upSendGen.io.frameReq.ready
+  // val isDownSendBusy = downSendGen.io.frameReq.ready
+  // val isUpSendBusy   =   upSendGen.io.frameReq.ready

  val isDownSendPend = RegInit(false.B)
  val isUpSendPend = RegInit(false.B)