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改6相位，从一个pll出，测试

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This commit is contained in:
Ruige Lee
2025-08-13 10:00:11 +08:00
parent cb2c4f46e5
commit 495a238a26
2 changed files with 7 additions and 7 deletions
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12
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase =>
//multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先
val multiCLK = IO(Input(Vec(16, Bool()))) val multiCLK = IO(Input(Vec(6, Bool())))
val sampleReg = Wire(Vec(23, Bool())) val sampleReg = Wire(Vec(9, Bool()))
for( i <- 0 until 16 ) { for( i <- 0 until 6 ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) } sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
} }
for( i <- 16 until 23 ){ for( i <- 6 until 9 ){
sampleReg(i) := withClockAndReset(multiCLK(i-8).asClock, reset.asBool){ RegNext(sampleReg(i-8))} sampleReg(i) := withClockAndReset(multiCLK(i-3).asClock, reset.asBool){ RegNext(sampleReg(i-3))}
} }
val asyncSerDat = PopCount(sampleReg) >= 12.U val asyncSerDat = PopCount(sampleReg) >= 5.U
// sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U

2
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{
val uDatIn = Input(Bool()) val uDatIn = Input(Bool())
val uDatOut = Output(Bool()) val uDatOut = Output(Bool())
val multiCLK = Input(Vec(16, Bool())) val multiCLK = Input(Vec(6, Bool()))
val iqspi = new QSPIInterfaceIO val iqspi = new QSPIInterfaceIO
val ospi = new SSPIInterfaceIO val ospi = new SSPIInterfaceIO