From 4919c357b3e41a4d6932b43f25b29b3f62fbdaf7 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 5 Aug 2025 17:11:09 +0800 Subject: [PATCH] =?UTF-8?q?FPGA=E9=A1=B6=E5=B1=82?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/resources/FPGATop_MP.v | 235 ++++++++++++++++++++++++++++++++ 1 file changed, 235 insertions(+) create mode 100644 src/main/resources/FPGATop_MP.v diff --git a/src/main/resources/FPGATop_MP.v b/src/main/resources/FPGATop_MP.v new file mode 100644 index 0000000..293d0f4 --- /dev/null +++ b/src/main/resources/FPGATop_MP.v @@ -0,0 +1,235 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2025/05/13 11:43:33 +// Design Name: +// Module Name: FPGATop +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module FPGATop( + input clkin, + input resetIn, + + input dDatIn_p, + input dDatIn_n, + + output dDatOut_p, + output dDatOut_n, + + input uDatIn_p, + input uDatIn_n, + + output uDatOut_p, + output uDatOut_n, + + input sck, + input mosi, + output miso, + input csn, + + input io_iqspi_sck, + inout [3:0] io_iqspi_data, + input io_iqspi_csn, + + output interrupt, + output [3:0] io_led + ); + +wire [15:0] multiCLK; + +wire reset; + +wire dDatIn; +wire dDatOut; +wire uDatIn; +wire uDatOut; + +wire clkin_bufg; + + BUFG BUFG_inst ( + .O(clkin_bufg), // 1-bit output: Clock output + .I(clkin) // 1-bit input: Clock input + ); + +clk_wiz_0 i_clk_0 + ( + .clk_out1(multiCLK[0]), + .clk_out2(multiCLK[1]), + .clk_out3(multiCLK[2]), + .clk_out4(multiCLK[3]), + .clk_out5(multiCLK[4]), + + .clk_in1(clkin_bufg) + ); + +clk_wiz_1 i_clk_1 + ( + .clk_out1(multiCLK[5]), + .clk_out2(multiCLK[6]), + .clk_out3(multiCLK[7]), + .clk_out4(multiCLK[8]), + .clk_out5(multiCLK[9]), + + .clk_in1(clkin_bufg) + ); + +clk_wiz_2 i_clk_2 + ( + .clk_out1(multiCLK[10]), + .clk_out2(multiCLK[11]), + .clk_out3(multiCLK[12]), + .clk_out4(multiCLK[13]), + .clk_out5(multiCLK[14]), + .clk_out6(multiCLK[15]), + + .clk_in1(clkin_bufg) + ); + +// proc_sys_reset_0 i_proc_sys_reset( +// .slowest_sync_clk(clk50M), +// .ext_reset_in(resetIn), +// .aux_reset_in(1'b0), +// .mb_debug_sys_rst(1'b0), +// .dcm_locked(1'b1), +// .mb_reset(), +// .bus_struct_reset(), +// .peripheral_reset(reset), +// .interconnect_aresetn(), +// .peripheral_aresetn() +// ); + +assign reset = resetIn; + +wire [3:0] iqspi_mosi; +wire [3:0] iqspi_miso; +wire iqspi_isDirIn; +wire isSoftReset; + +wire [7:0] led; + +ShinTop i_ShinTop( + .clock(multiCLK[0]), + .reset(reset | isSoftReset), + .io_dDatIn(dDatIn), + .io_dDatOut(dDatOut), + .io_uDatIn(uDatIn), + .io_uDatOut(uDatOut), + + .io_multiCLK_0(multiCLK[0]), + .io_multiCLK_1(multiCLK[1]), + .io_multiCLK_2(multiCLK[2]), + .io_multiCLK_3(multiCLK[3]), + .io_multiCLK_4(multiCLK[4]), + .io_multiCLK_5(multiCLK[5]), + .io_multiCLK_6(multiCLK[6]), + .io_multiCLK_7(multiCLK[7]), + .io_multiCLK_8(multiCLK[8]), + .io_multiCLK_9(multiCLK[9]), + .io_multiCLK_10(multiCLK[10]), + .io_multiCLK_11(multiCLK[11]), + .io_multiCLK_12(multiCLK[12]), + .io_multiCLK_13(multiCLK[13]), + .io_multiCLK_14(multiCLK[14]), + .io_multiCLK_15(multiCLK[15]), + + .io_iqspi_sck(io_iqspi_sck), + .io_iqspi_mosi(iqspi_mosi), + .io_iqspi_miso(iqspi_miso), + .io_iqspi_isDirIn(iqspi_isDirIn), + .io_iqspi_csn(io_iqspi_csn), + .io_ospi_sck(sck), + .io_ospi_mosi(mosi), + .io_ospi_miso(miso), + .io_ospi_csn(csn), + .io_oqspi_sck(1'b0), + .io_oqspi_mosi(4'b0), + .io_oqspi_miso(), + .io_oqspi_isDirIn(), + .io_oqspi_csn(1'b1), + + .io_iSync_0(), + .io_iSync_1(), + .io_iSync_2(), + .io_iSync_3(), + .io_oSync_0(), + .io_oSync_1(), + .io_oSync_2(), + .io_oSync_3(), + + .io_isSoftReset(isSoftReset), + .io_ledTest(led), + .io_interrupt(interrupt), + + .io_latchPin_0(1'b0), + .io_latchPin_1(1'b0) +); + + + assign io_led = led[5:2]; + + + IOBUF QSPI_D0_inst ( + .O(iqspi_mosi[0]), // Buffer output + .IO(io_iqspi_data[0]), // Buffer inout port (connect directly to top-level port) + .I(iqspi_miso[0]), // Buffer input + .T(iqspi_isDirIn) // 3-state enable input, high=input, low=output + ); + + IOBUF QSPI_D1_inst ( + .O(iqspi_mosi[1]), // Buffer output + .IO(io_iqspi_data[1]), // Buffer inout port (connect directly to top-level port) + .I(iqspi_miso[1]), // Buffer input + .T(iqspi_isDirIn) // 3-state enable input, high=input, low=output + ); + IOBUF QSPI_D2_inst ( + .O(iqspi_mosi[2]), // Buffer output + .IO(io_iqspi_data[2]), // Buffer inout port (connect directly to top-level port) + .I(iqspi_miso[2]), // Buffer input + .T(iqspi_isDirIn) // 3-state enable input, high=input, low=output + ); + + IOBUF QSPI_D3_inst ( + .O(iqspi_mosi[3]), // Buffer output + .IO(io_iqspi_data[3]), // Buffer inout port (connect directly to top-level port) + .I(iqspi_miso[3]), // Buffer input + .T(iqspi_isDirIn) // 3-state enable input, high=input, low=output + ); + + IBUFDS i_dDatIn ( + .O(dDatIn), // Buffer output + .I(dDatIn_p), // Diff_p buffer input (connect directly to top-level port) + .IB(dDatIn_n) // Diff_n buffer input (connect directly to top-level port) + ); + + IBUFDS i_uDatIn ( + .O(uDatIn), // Buffer output + .I(uDatIn_p), // Diff_p buffer input (connect directly to top-level port) + .IB(uDatIn_n) // Diff_n buffer input (connect directly to top-level port) + ); + + OBUFDS i_dDatOut ( + .O(dDatOut_p), // Diff_p output (connect directly to top-level port) + .OB(dDatOut_n), // Diff_n output (connect directly to top-level port) + .I(dDatOut) // Buffer input + ); + + OBUFDS i_uDatOut ( + .O(uDatOut_p), // Diff_p output (connect directly to top-level port) + .OB(uDatOut_n), // Diff_n output (connect directly to top-level port) + .I(uDatOut) // Buffer input + ); +endmodule