diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 5c39310..61bd9bb 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -552,15 +552,6 @@ trait SlaveParserRW{ this: SlaveParserBase =>
 
   val upTransLenCnt = RegInit(0.U)
 
-  //读出uSM  
-  val isRead = 
-    ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
-      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
-      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
-      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR )                                             ) |
-      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR )                                             )
-    )
-  )
 
   val addrr = Reg(UInt(15.W))  
   val logicAddrrNext = Wire( UInt(30.W) )
@@ -613,8 +604,24 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   val isRDSM5 = addrr(14,11) === "b0110".U
   val isRDSM7 = addrr(14,11) === "b1000".U
 
-  val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) |
-      upRecParser.io.data.fire )
+
+  val isSeqRead = 
+    ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
+      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) )) |
+      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) )) |
+      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR )                                             ) |
+      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR )                                             )
+    )
+  ) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
+
+  val isLgcRead = 
+    ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
+      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
+      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
+    )
+  ) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )
+
+  val isLvdsEnR = isSeqRead | isLgcRead 
 
   when( upRecParser.io.subMsgReq.fire){
     when(
@@ -625,14 +632,20 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
       addrr := acquireUpPhyAddrr
     }
-  } .elsewhen( upRecParser.io.data.fire ){
+  } .elsewhen( isUpLgcAddrrAcquireTrans ){
+    when( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
+      addrr := acquireUpPhyAddrr
+    }
+  }
+  .elsewhen( isLvdsEnR ){
+    assert(~isUpLgcAddrrAcquireTrans)
     when( 
       ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD   | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
       ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
     ){
       addrr := addrr + 1.U
     } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
-      addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrrAcquireTrans, acquireUpPhyAddrr, 0.U), addrr + 1.U )
+      addrr := Mux( upTransLenCnt === 0.U, 0.U, addrr + 1.U )
     }
   }