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tx: big-endian to little-endian

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This commit is contained in:
RuigeLee
2023-09-19 17:54:36 +08:00
parent 40b558d3a2
commit 4702991e69
2 changed files with 11 additions and 11 deletions
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4
src/main/scala/mac/MAC.scala
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@@ -492,7 +492,7 @@ dontTouch(Collision )
dontTouch(CarrierSense_Tx2) dontTouch(CarrierSense_Tx2)
dontTouch(RxEnSync ) dontTouch(RxEnSync )
printf("Warning! clock doesn't switch when loopBck!")
// Muxed MII receive data valid // Muxed MII receive data valid
MRxDV_Lb := Mux(r_LoopBck, io.mtxen_pad_o, io.mrxdv_pad_i & RxEnSync) MRxDV_Lb := Mux(r_LoopBck, io.mtxen_pad_o, io.mrxdv_pad_i & RxEnSync)
@@ -529,7 +529,7 @@ txethmac.io.ExDfrEn := r_ExDfrEn
io.mtxd_pad_o := txethmac.io.MTxD io.mtxd_pad_o := txethmac.io.MTxD
io.mtxen_pad_o := txethmac.io.MTxEn io.mtxen_pad_o := txethmac.io.MTxEn
io. mtxerr_pad_o := txethmac.io.MTxErr io.mtxerr_pad_o := txethmac.io.MTxErr
TxDoneIn := txethmac.io.TxDone TxDoneIn := txethmac.io.TxDone
TxRetry := txethmac.io.TxRetry TxRetry := txethmac.io.TxRetry
TxAbortIn := txethmac.io.TxAbort TxAbortIn := txethmac.io.TxAbort

18
src/main/scala/mac/MacTilelink.scala
View File

@@ -1206,19 +1206,19 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
// Tx data selection (latching) // Tx data selection (latching)
when( TxStartFrm_sync & ~TxStartFrm ){ when( TxStartFrm_sync & ~TxStartFrm ){
TxData := Mux1H(Seq( TxData := Mux1H(Seq(
( TxPointerLSB === 0.U ) -> TxData_wb(31,24),// Big Endian Byte Ordering ( TxPointerLSB === 0.U ) -> TxData_wb( 7, 0),// little Endian Byte Ordering
( TxPointerLSB === 1.U ) -> TxData_wb(23,16),// Big Endian Byte Ordering ( TxPointerLSB === 1.U ) -> TxData_wb(15, 8),// little Endian Byte Ordering
( TxPointerLSB === 2.U ) -> TxData_wb(15, 8),// Big Endian Byte Ordering ( TxPointerLSB === 2.U ) -> TxData_wb(23,16),// little Endian Byte Ordering
( TxPointerLSB === 3.U ) -> TxData_wb( 7, 0),// Big Endian Byte Ordering ( TxPointerLSB === 3.U ) -> TxData_wb(31,24),// little Endian Byte Ordering
)) ))
} .elsewhen( TxStartFrm & io.TxUsedData & TxPointerLSB === 3.U ){ } .elsewhen( TxStartFrm & io.TxUsedData & TxPointerLSB === 3.U ){
TxData := TxData_wb(31,24) // Big Endian Byte Ordering TxData := TxData_wb( 7, 0) // little Endian Byte Ordering
} .elsewhen(io.TxUsedData & Flop){ } .elsewhen(io.TxUsedData & Flop){
TxData := Mux1H(Seq( TxData := Mux1H(Seq(
(TxByteCnt === 0.U) -> TxDataLatched(31,24),// Big Endian Byte Ordering (TxByteCnt === 0.U) -> TxDataLatched( 7, 0),// little Endian Byte Ordering
(TxByteCnt === 1.U) -> TxDataLatched(23,16), (TxByteCnt === 1.U) -> TxDataLatched(15, 8),
(TxByteCnt === 2.U) -> TxDataLatched(15, 8), (TxByteCnt === 2.U) -> TxDataLatched(23,16),
(TxByteCnt === 3.U) -> TxDataLatched( 7, 0), (TxByteCnt === 3.U) -> TxDataLatched(31,24),
)) ))
} }