From 46cbd6edecc5ec2554613355b5c83ab25c36b84d Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 4 Mar 2025 12:01:47 +0800 Subject: [PATCH] rxFifo bypass to txFifo --- src/main/scala/backBoard/ebus/RoCC2CDR.scala | 146 +++++++++++++------ 1 file changed, 103 insertions(+), 43 deletions(-) diff --git a/src/main/scala/backBoard/ebus/RoCC2CDR.scala b/src/main/scala/backBoard/ebus/RoCC2CDR.scala index 894926a..22c6208 100644 --- a/src/main/scala/backBoard/ebus/RoCC2CDR.scala +++ b/src/main/scala/backBoard/ebus/RoCC2CDR.scala @@ -77,6 +77,7 @@ abstract class RoCC2CDRImplBase(outer: RoCC2CDR)(implicit p: Parameters) extends val wdata = Wire(UInt(32.W)) + val isTLReadRxFifoBypassTx = for( i <- 0 until 4 ) yield { Wire(Bool()) } //0 rx0->tx0, 1 rx0->tx1, 2 rx1 -> tx0, 3 rx1 ->tx1 } @@ -144,9 +145,23 @@ trait RoCC2CDRImplTx{ this: RoCC2CDRImplBase => txLen(i) := txLen(i) - 1.U } - txFifo(i).io.enq.bits := wdata - txFifo(i).io.enq.valid := isTLWriteTxFifo(i) & txLen(i) =/= 0.U + txFifo(i).io.enq.bits := Mux1H(Seq( + isTLWriteTxFifo(i) -> wdata, + isTLReadRxFifoBypassTx(0+i) -> rxFifo(0).io.deq.bits, + isTLReadRxFifoBypassTx(2+i) -> rxFifo(1).io.deq.bits, + )) + + +//0 rx0->tx0, 1 rx0->tx1, 2 rx1 -> tx0, 3 rx1 ->tx1 + + txFifo(i).io.enq.valid := + txLen(i) =/= 0.U & ( + isTLWriteTxFifo(i) | + isTLReadRxFifoBypassTx(0+i) | + isTLReadRxFifoBypassTx(2+i) + ) + when( isTLWriteSoftReset(0+i) ){ txLeft(i) := 0.U } .elsewhen( txFifo(i).io.enq.fire & txFifo(i).io.deq.fire ){ @@ -393,54 +408,94 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer isTLClearTimeOut(1) := io.cmd.fire & io.cmd.bits.inst.funct === 9.U & io.cmd.bits.inst.xs1 isTLReadTimeOut(1) := io.cmd.fire & io.cmd.bits.inst.funct === 9.U & io.cmd.bits.inst.xd +//0 rx0->tx0, 1 rx0->tx1, 2 rx1 -> tx0, 3 rx1 ->tx1 isTLWriteSoftReset(2) := io.cmd.fire & io.cmd.bits.inst.funct === 10.U isTLReadRxLen(0) := io.cmd.fire & io.cmd.bits.inst.funct === 11.U isTLReadRxFifo(0) := io.cmd.fire & io.cmd.bits.inst.funct === 12.U - isTLReadRxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 13.U - isTLWriteLimitTimerAim(0) := io.cmd.fire & io.cmd.bits.inst.funct === 14.U - isTLWriteLimitTxPair(0) := io.cmd.fire & io.cmd.bits.inst.funct === 15.U + isTLReadRxFifoBypassTx(0) := io.cmd.fire & io.cmd.bits.inst.funct === 13.U + isTLReadRxFifoBypassTx(1) := io.cmd.fire & io.cmd.bits.inst.funct === 14.U + isTLReadRxCrc(0) := io.cmd.fire & io.cmd.bits.inst.funct === 15.U + isTLWriteLimitTimerAim(0) := io.cmd.fire & io.cmd.bits.inst.funct === 16.U + isTLWriteLimitTxPair(0) := io.cmd.fire & io.cmd.bits.inst.funct === 17.U - isTLWriteSoftReset(3) := io.cmd.fire & io.cmd.bits.inst.funct === 16.U - isTLReadRxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 17.U - isTLReadRxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 18.U - isTLReadRxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 19.U - isTLWriteLimitTimerAim(1) := io.cmd.fire & io.cmd.bits.inst.funct === 20.U - isTLWriteLimitTxPair(1) := io.cmd.fire & io.cmd.bits.inst.funct === 21.U + isTLWriteSoftReset(3) := io.cmd.fire & io.cmd.bits.inst.funct === 18.U + isTLReadRxLen(1) := io.cmd.fire & io.cmd.bits.inst.funct === 19.U + isTLReadRxFifo(1) := io.cmd.fire & io.cmd.bits.inst.funct === 20.U + isTLReadRxFifoBypassTx(2) := io.cmd.fire & io.cmd.bits.inst.funct === 21.U + isTLReadRxFifoBypassTx(3) := io.cmd.fire & io.cmd.bits.inst.funct === 22.U + isTLReadRxCrc(1) := io.cmd.fire & io.cmd.bits.inst.funct === 23.U + isTLWriteLimitTimerAim(1) := io.cmd.fire & io.cmd.bits.inst.funct === 24.U + isTLWriteLimitTxPair(1) := io.cmd.fire & io.cmd.bits.inst.funct === 25.U - isTLReadStatus := io.cmd.fire & io.cmd.bits.inst.funct === 22.U - val isTLReadInterrupt = io.cmd.fire & io.cmd.bits.inst.funct === 23.U & io.cmd.bits.inst.xd - val isTLClearInterrupt = io.cmd.fire & io.cmd.bits.inst.funct === 23.U & io.cmd.bits.inst.xs1 - isReadIsLast := io.cmd.fire & io.cmd.bits.inst.funct === 24.U + isTLReadStatus := io.cmd.fire & io.cmd.bits.inst.funct === 26.U + val isTLReadInterrupt = io.cmd.fire & io.cmd.bits.inst.funct === 27.U & io.cmd.bits.inst.xd + val isTLClearInterrupt = io.cmd.fire & io.cmd.bits.inst.funct === 28.U & io.cmd.bits.inst.xs1 + val isTLWriteIntMask = io.cmd.fire & io.cmd.bits.inst.funct === 29.U + isReadIsLast := io.cmd.fire & io.cmd.bits.inst.funct === 30.U + + + + + + val interruptReg = RegInit(0.U(32.W)) + val interruptMask = RegEnable(wdata, 0.U(32.W), isTLWriteIntMask) + + val statusRxStart = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val statusRxEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val statusTxEnd = for( i <- 0 until 2 ) yield { RegInit(false.B) } + + for( i <- 0 until 2 ){ + + when( isTLWriteSoftReset(2+i) ){ + statusRxStart(i) := false.B + } .elsewhen( intRxStart(i) ){ + statusRxStart(i) := true.B + } + + when( isTLWriteSoftReset(2+i) ){ + statusRxEnd(i) := false.B + } .elsewhen( intRxEnd(i) ){ + statusRxEnd(i) := true.B + } + + when( isTLWriteSoftReset(0+i) ){ + statusTxEnd(i) := false.B + } .elsewhen( intTxEnd(i) ){ + statusTxEnd(i) := true.B + } + } - val interruptReg = RegInit(0.U(32.W)) when(true.B){ - interruptReg := (interruptReg & Mux( isTLClearInterrupt, ~wdata, "hFFFFFFFF".U)) | Cat( - intTxEnd(1), intTxEnd(0), - intRxError(1), intRxError(0), - intRxStart(1), intRxStart(0), - intRxEnd(1), intRxEnd(0), - intTxFifoDeq(1), intTxFifoDeq(0), - intRxFifoEnq(1), intRxFifoEnq(0) - ) + interruptReg := + ( + (interruptReg & Mux( isTLClearInterrupt, ~wdata, "hFFFFFFFF".U)) | Cat( + intTxEnd(1), intTxEnd(0), + intRxError(1), intRxError(0), + intRxStart(1), intRxStart(0), + intRxEnd(1), intRxEnd(0), + intTxFifoDeq(1), intTxFifoDeq(0), + intRxFifoEnq(1), intRxFifoEnq(0) + ) + ) & interruptMask } io.interrupt := - intTxEnd(0) | - intTxEnd(1) | - intRxError(0) | - intRxError(1) | - intRxStart(0) | - intRxStart(1) | - intRxEnd(0) | - intRxEnd(1) | - intTxFifoDeq(0) | - intTxFifoDeq(1) | - intRxFifoEnq(0) | - intRxFifoEnq(1) + ( intTxEnd(1) & interruptMask.extract(11) ) | + ( intTxEnd(0) & interruptMask.extract(10) ) | + ( intRxError(1) & interruptMask.extract( 9) ) | + ( intRxError(0) & interruptMask.extract( 8) ) | + ( intRxStart(1) & interruptMask.extract( 7) ) | + ( intRxStart(0) & interruptMask.extract( 6) ) | + ( intRxEnd(1) & interruptMask.extract( 5) ) | + ( intRxEnd(0) & interruptMask.extract( 4) ) | + ( intTxFifoDeq(1) & interruptMask.extract( 3) ) | + ( intTxFifoDeq(0) & interruptMask.extract( 2) ) | + ( intRxFifoEnq(1) & interruptMask.extract( 1) ) | + ( intRxFifoEnq(0) & interruptMask.extract( 0) ) wdata := io.cmd.bits.rs1 @@ -475,16 +530,21 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer + when( isTLReadStatus ){ - rdata := Cat( txLeft(1), txLeft(0), rxLeft(1), rxLeft(0), isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), isTxBusy(1), isTxBusy(0), isTxFull(1), isTxFull(0) ) - } .elsewhen(isTLReadRxLen(0) ){ + rdata := Cat( + txLeft(1), txLeft(0), rxLeft(1), rxLeft(0), + isRxValid(1), isRxValid(0), isRxError(1), isRxError(0), + statusRxStart(1), statusRxStart(0), statusRxEnd(1), statusRxEnd(0), statusTxEnd(1), statusTxEnd(0) + ) + } .elsewhen(isTLReadRxLen(0) ){ rdata := rxLen(0) - } .elsewhen(isTLReadRxLen(1) ){ + } .elsewhen(isTLReadRxLen(1) ){ rdata := rxLen(1) - } .elsewhen(isTLReadRxFifo(0) ){ + } .elsewhen(isTLReadRxFifo(0) | isTLReadRxFifoBypassTx(0) | isTLReadRxFifoBypassTx(1) ){ rdata := rxFifo(0).io.deq.bits - } .elsewhen(isTLReadRxFifo(1) ){ + } .elsewhen(isTLReadRxFifo(1) | isTLReadRxFifoBypassTx(2) | isTLReadRxFifoBypassTx(3) ){ rdata := rxFifo(1).io.deq.bits } .elsewhen(isReadIsLast){ rdata := cdrInio.isLast @@ -513,9 +573,9 @@ with RoCC2CDRImplLimitTimmer with RoCC2CDRImplOutTimmer respValid := true.B } .elsewhen(isTLReadRxLen(1) ){ respValid := true.B - } .elsewhen(isTLReadRxFifo(0) ){ + } .elsewhen(isTLReadRxFifo(0) | isTLReadRxFifoBypassTx(0) | isTLReadRxFifoBypassTx(1) ){ respValid := true.B - } .elsewhen(isTLReadRxFifo(1) ){ + } .elsewhen(isTLReadRxFifo(1) | isTLReadRxFifoBypassTx(2) | isTLReadRxFifoBypassTx(3) ){ respValid := true.B } .elsewhen(isReadIsLast){ respValid := true.B