恢复ebus工程

src/main/scala/backBoard/ebus/BackBoardMst.scala

@@ -0,0 +1,52 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class BackBoardMstIO extends Bundle{
+  val downStreamReqDat  = Input( Bool() )
+  val downStreamRespdat = Output(Bool())
+
+  val CS   = Input(Bool())
+  val MISO = Output(Bool())
+  val MOSI = Input(Bool())
+  val SCK  = Input(Bool())
+
+  val interrupt = Output(Bool())
+
+  val clk4            = Input( Bool() )
+
+}
+
+
+class BackBoardMst extends Module{
+  val io: BackBoardMstIO = IO(new BackBoardMstIO)
+
+
+    val spi = Module( new SpiSlv )
+    val in  = Module( new CDR4MultiIn )
+    val out = Module( new CDROutBus )
+
+    spi.io.CS   := io.CS
+    io.MISO     := spi.io.MISO
+    spi.io.MOSI := io.MOSI
+    spi.io.SCK := io.SCK
+
+    // io.interrupt := spi.io.interrupt
+    io.interrupt := false.B
+
+    spi.io.CDRIn  <> in.io.latDat
+    spi.io.CDROut <> out.io.pkgDat
+
+    in.io.clk4 := io.clk4
+    spi.io.clk4 := io.clk4
+
+    in.io.dat  := io.downStreamReqDat
+    io.downStreamRespdat := out.io.dat
+
+
+}
+
+
+

src/main/scala/backBoard/ebus/BackBoardSlv.scala

@@ -0,0 +1,105 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class BackBoardSlvIO extends Bundle{
+  val localHost = Input(UInt(5.W))
+
+  val upStreamReqDat    = Input( Bool() )
+  val downStreamReqDat  = Input( Bool() )
+
+  val upStreamRespdat   = Output(Bool())
+  val downStreamRespdat = Output(Bool())
+
+  val clk4            = Input( Bool() )
+}
+
+
+abstract class BackBoardSlvBase extends Module{
+  val io: BackBoardSlvIO = IO(new BackBoardSlvIO)
+
+
+  val upStreamReq    = Module(new CDR4MultiIn)
+  val downStreamReq  = Module(new CDR4MultiIn)
+
+  val upStreamResp   = Module(new CDROutBus)
+  val downStreamResp = Module(new CDROutBus)
+
+  upStreamReq.io.clk4   := io.clk4
+  downStreamReq.io.clk4 := io.clk4
+  upStreamReq.io.dat      := io.upStreamReqDat
+  downStreamReq.io.dat    := io.downStreamReqDat
+
+  io.upStreamRespdat   := upStreamResp.io.dat
+  io.downStreamRespdat := downStreamResp.io.dat
+
+
+
+  def IDLE            = 0.U
+  def UPSTREAM_RESP   = 1.U
+  def DOWNSTREAM_RESP = 2.U
+
+  val stateNext = Wire( UInt(2.W) )
+  val stateCurr = RegNext(stateNext, 0.U)
+
+  stateNext := Mux1H(Seq(
+    (stateCurr === IDLE)            -> Mux(upStreamReq.io.latDat.fire, Mux(upStreamReq.io.latDat.bits.address(5,1) === io.localHost, UPSTREAM_RESP, DOWNSTREAM_RESP), Mux(downStreamReq.io.latDat.fire, UPSTREAM_RESP, IDLE) ),
+    (stateCurr === UPSTREAM_RESP)   -> Mux(upStreamResp.io.pkgDat.fire,   IDLE, UPSTREAM_RESP ),
+    (stateCurr === DOWNSTREAM_RESP) -> Mux(downStreamResp.io.pkgDat.fire, IDLE, DOWNSTREAM_RESP ),
+  ))
+
+  val upStreamReqReady    = RegInit(false.B); upStreamReq.io.latDat.ready   := upStreamReqReady
+  val downStreamReqReady  = RegInit(false.B); downStreamReq.io.latDat.ready := downStreamReqReady
+
+  val upStreamRespValid   = RegInit(false.B); upStreamResp.io.pkgDat.valid := upStreamRespValid
+  val upStreamRespInfo    = Reg(new CDRData); upStreamResp.io.pkgDat.bits  := upStreamRespInfo
+  val downStreamRespValid = RegInit(false.B); downStreamResp.io.pkgDat.valid := downStreamRespValid
+  val downStreamRespInfo  = Reg(new CDRData); downStreamResp.io.pkgDat.bits  := downStreamRespInfo
+
+  val registersRD = Wire(UInt(32.W))
+
+
+
+}
+
+trait StatusControl{ this: BackBoardSlvBase =>
+
+  when( upStreamResp.io.pkgDat.fire ){
+    upStreamRespValid := false.B
+  } .elsewhen( downStreamResp.io.pkgDat.fire ){
+    downStreamRespValid := false.B
+  }.elsewhen( upStreamReq.io.latDat.fire ){
+    upStreamReqReady := false.B
+
+    when( upStreamReq.io.latDat.bits.address(5,1) === io.localHost ){
+      upStreamRespValid := true.B
+      upStreamRespInfo.address  := upStreamReq.io.latDat.bits.address
+      upStreamRespInfo.register := upStreamReq.io.latDat.bits.register
+      upStreamRespInfo.data     := Mux(upStreamReq.io.latDat.bits.address.extract(0) === 0.U, registersRD, 0.U ) 
+      upStreamRespInfo.hash     := 0.U
+
+    } .otherwise{
+      downStreamRespValid := true.B
+      downStreamRespInfo  := upStreamReq.io.latDat.bits
+    }
+
+  } .elsewhen( downStreamReq.io.latDat.fire ){
+    downStreamReqReady := false.B
+
+    upStreamRespValid := true.B
+    upStreamRespInfo  := downStreamReq.io.latDat.bits
+  } .elsewhen( downStreamReq.io.latDat.valid & ~downStreamReq.io.latDat.ready && stateCurr === IDLE ){
+    downStreamReqReady := true.B
+  } .elsewhen( upStreamReq.io.latDat.valid & ~upStreamReq.io.latDat.ready & ~downStreamReq.io.latDat.valid & stateCurr === IDLE ){
+    upStreamReqReady := true.B
+  }
+
+
+
+}
+
+
+class BackBoardSlv extends BackBoardSlvBase with StatusControl with LocalRegisters
+

src/main/scala/backBoard/ebus/CDR4MultiIn.scala

@@ -0,0 +1,82 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+import freechips.rocketchip.util._
+
+
+class CDRData extends Bundle{
+  val address  = UInt(6.W)
+  val register = UInt(8.W)
+  val data     = UInt(32.W)
+  val hash     = UInt(16.W)
+
+  def crcHash = 0.U
+  def isHashPass = true.B
+
+}
+
+class CDR4MultiInIO() extends Bundle{
+  val dat = Input(Bool())
+  val clk4 = Input(Bool())
+
+  val latDat = Decoupled(new CDRData)
+}
+
+
+
+class CDR4MultiIn() extends Module{
+  val io: CDR4MultiInIO = IO(new CDR4MultiInIO())
+
+  val latValidSet = Wire(Bool())
+
+  val latValidSetAsync = ShiftRegister( latValidSet, 2, false.B, true.B )
+  val latValidReset    = RegNext(latValidSetAsync, false.B)
+
+  val transInfo = Wire(new CDRData)
+
+  withClockAndReset( io.clk4.asClock, reset ){
+    val latValidSetReg     = RegInit(false.B); latValidSet := latValidSetReg
+    val latValidResetAsync = ShiftRegister(latValidReset, 2, false.B, true.B)
+
+    val shiftDat = RegInit( 0.U( ((1+6+8+32+16)*4+2).W ) )
+
+
+    transInfo := 
+      Cat(
+        ( 0 until (6+8+32+16) ).map{ i => shiftDat( 4*(i+1) + 1 ) }
+      ).asTypeOf(new CDRData)
+
+
+    when( latValidSetReg & latValidResetAsync ){
+      shiftDat := 0.U
+      latValidSetReg := false.B
+    } .elsewhen( shiftDat.extract(0) =/= 1.U ){
+      shiftDat := Cat(io.dat, shiftDat( ((1+6+8+32+16)*4+2)-1, 1) ) 
+    } .elsewhen( shiftDat.extract(0) === 1.U ){
+      latValidSetReg := true.B
+    }
+
+
+  }
+
+  val latDatValid = RegInit(false.B)
+  val latDatInfo  = Reg(new CDRData)
+
+  when( io.latDat.fire ){
+    latDatValid := false.B
+  } .elsewhen( latValidSetAsync & ~latValidReset){
+    latDatValid := true.B
+    latDatInfo  := transInfo
+  }
+
+  io.latDat.valid := latDatValid
+  io.latDat.bits  := latDatInfo
+
+
+}
+
+

src/main/scala/backBoard/ebus/CDROutBus.scala

@@ -0,0 +1,65 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class CDROutBusIO() extends Bundle{
+  val pkgDat = Flipped(Decoupled(new CDRData))
+  val dat    = Output(Bool())
+
+}
+
+class CDROutBus extends Module{
+  val io: CDROutBusIO = IO(new CDROutBusIO)
+
+  val isBusy = RegInit(false.B)
+  io.pkgDat.ready := ~isBusy
+  
+  val address  = Reg(UInt(6.W))
+  val register = Reg(UInt(8.W))
+  val data     = Reg(UInt(32.W))
+  val hash     = Reg(UInt(16.W))
+
+  val cnt = RegInit( 0.U(7.W) )
+
+
+  when( cnt === (1+6+8+32+16).U ){
+    isBusy := false.B
+  } .elsewhen( io.pkgDat.fire ){
+    isBusy := true.B
+
+    address  := io.pkgDat.bits.address
+    register := io.pkgDat.bits.register
+    data     := io.pkgDat.bits.data
+
+  }
+
+  when(io.pkgDat.fire){
+    cnt := 0.U
+  } .elsewhen( isBusy ){
+    cnt := cnt + 1.U
+  }
+
+
+
+  when( cnt === 1.U ){
+    io.dat := true.B
+  } .elsewhen( cnt >= (1 + 1).U && cnt < (6 + 1 + 1).U ){
+    io.dat := address(5)
+    address := address << 1
+  } .elsewhen( cnt >= (1 + 1 + 6).U && cnt < (8 + 1+ 1 + 6).U ){
+    io.dat := register(7)
+    register := register << 1
+  } .elsewhen( cnt >= (1 + 1 + 6 + 8).U && cnt < (32 + 1 + 1 + 6 + 8).U ){
+    io.dat := data(31)
+    data := data << 1
+  } .elsewhen( cnt >= (1 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 1 + 6 + 8 + 32).U ){
+    io.dat := hash(15)
+    hash := hash << 1
+  } .otherwise{
+    io.dat := false.B
+  }
+
+}
+

src/main/scala/backBoard/ebus/FSMC.scala

@@ -0,0 +1,42 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+
+
+
+
+class FSMCSlvIO extends Bundle{
+  val FSMC = new FSMC_Port_Bundle
+
+  val CDRIn  = Flipped(Valid(new CDRData))
+  val CDROut = Valid(new CDRData)
+}
+
+class FSMCSlvBase extends Module{
+  val io: FSMCSlvIO = IO(new FSMCSlvIO)
+
+
+
+
+
+
+
+
+
+
+  mirror.io.datar_b,
+  mirror.io.ce_b,
+  mirror.io.we_b,
+  mirror.io.[10:0] addr_b,
+  mirror.io.[7:0] dataw_b
+}
+
+trait MirrorSRAM { this: FSMCSlvBase =>
+
+
+}
+
+

src/main/scala/backBoard/ebus/SpiSlv.scala

@@ -0,0 +1,89 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+class CDR_Master_Interface_Bundle extends CDRData{
+  val op       = UInt(2.W)
+}
+
+class SpiSlvIO extends Bundle{
+  val CS   = Input(Bool())
+  val MISO = Output(Bool())
+  val MOSI = Input(Bool())
+  val SCK  = Input(Bool())
+
+  val clk4 = Input(Bool())
+
+  val CDRIn  = Flipped(Decoupled(new CDRData))
+  val CDROut = Decoupled(new CDRData)
+
+}
+
+class SpiSlv extends Module{
+  val io: SpiSlvIO = IO(new SpiSlvIO)
+
+  val CDROutValidSet      = Wire(Bool())
+  val CDROutValidSetAsync = ShiftRegister(CDROutValidSet, 2, false.B, true.B)
+  val CDROutValidReset    = RegNext(CDROutValidSetAsync, false.B)
+
+  // val CDRInValidSet = RegInit(false.B)
+  val CDRInValidReset = Wire(Bool())
+  val CDRInValidResetAsync = ShiftRegister( CDRInValidReset, 2, false.B, true.B)
+
+  val cent = Wire(new CDR_Master_Interface_Bundle)
+  withClockAndReset( io.clk4.asClock, reset ){
+    val centReg = RegInit(0.U.asTypeOf(new CDR_Master_Interface_Bundle)); cent := centReg
+    val sckShift = ShiftRegisters( io.SCK, 3, false.B, true.B )
+    val csShift  = ShiftRegisters( io.CS, 3, true.B, true.B )
+    val mosiShift  = ShiftRegisters( io.MOSI, 2, true.B, true.B )
+
+
+    val CDROutValidSetReg        = RegInit(false.B); CDROutValidSet := CDROutValidSetReg
+    val CDROutValidResetAsync = ShiftRegister( CDROutValidReset, 2, false.B, true.B )
+
+    val CDRInValidSetAsync = ShiftRegister( io.CDRIn.valid , 2, false.B, true.B )
+    val CDRInValidResetReg = RegNext(CDRInValidSetAsync & csShift(1) & ~CDROutValidSetReg, false.B); CDRInValidReset := CDRInValidResetReg
+
+    when( CDROutValidSetReg & CDROutValidResetAsync ){
+      CDROutValidSetReg := false.B
+      centReg.op := 1.U
+    } .elsewhen( ~csShift(2) & csShift(1) ){
+      CDROutValidSetReg := true.B
+    }
+
+    io.MISO := centReg.asUInt.extract( 6+8+32+2+16-1 )
+
+    val sckPosedge = ~sckShift(2) & sckShift(1)
+    val sckNegedge = sckShift(2) & ~sckShift(1)
+
+    when( ~csShift(1) ){
+      when( sckPosedge ){
+        centReg := Cat(centReg.asUInt( 6+8+32+2+16-2, 0 ), mosiShift(1)).asTypeOf(new CDR_Master_Interface_Bundle)
+      }
+    } .otherwise{
+      when( CDRInValidSetAsync & ~CDROutValidSetReg ){
+        centReg.address  := io.CDRIn.bits.address
+        centReg.register := io.CDRIn.bits.register
+        centReg.data     := io.CDRIn.bits.data
+        centReg.op       := 0.U
+      }
+    }
+  }
+
+  val CDROutValid = RegInit(false.B); io.CDROut.valid := CDROutValid
+  val CDROutInfo  = Reg(new CDRData); io.CDROut.bits  := CDROutInfo
+
+  when( io.CDROut.fire ){
+    CDROutValid := false.B
+  } .elsewhen( CDROutValidSet & ~CDROutValidSetAsync ){
+    CDROutValid := true.B
+    CDROutInfo  := cent
+  }
+
+  io.CDRIn.ready := CDRInValidResetAsync
+
+}
+
+