From 45e46b2d46dc9998cb4193f458e8b6af51259de5 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Thu, 16 May 2024 16:07:50 +0800
Subject: [PATCH] =?UTF-8?q?=E6=B5=8B=E8=AF=95=EF=BC=9A=E4=BB=8E=E6=9C=BACD?=
 =?UTF-8?q?R=E9=94=99=E8=AF=AFIO=E8=A1=A8=E7=A4=BA?=
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---
 src/main/scala/backBoard/LocalRegisters.scala | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 34d5ee0..d6632ac 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -287,7 +287,22 @@ with BackBoardSlvOut16{
     upReg(7) := valueReg(15,8)
   }
 
-  out := outPin
+  // out := outPin
+
+  val isDownCDR = RegInit(false.B)
+  val isUpCDR   = RegInit(false.B)
+
+  when( isCrcPass ){
+    isDownCDR := false.B
+    isUpCDR   := false.B
+  } .elsewhen( lvdsSlv.io.downstream_rx_cdr_err ){
+    isDownCDR := true.B
+  } .elsewhen( lvdsSlv.io.upstream_rx_cdr_err ){
+    isUpCDR   := true.B
+  }
+
+  //override
+  out := Mux( isDownCDR & isUpCDR, "h5555".U, Mux(isDownCDR, Cat(Fill(16, flash1HZ)), Mux( isUpCDR, Cat(Fill(16, flash2HZ)), outPin )))
 
 
 }