转发功能已经调通

Makefile

@@ -46,7 +46,10 @@ testShin:
 	-y ./generated/shin \
 	-I ./generated/shin \
 	./tb/shinTest/SlaveParserTb.v 
-	vvp.exe  -N ./build/shinTest.iverilog -lxt2
+	vvp  -N ./tb/build/shinTest.iverilog -lxt2
+
+vcdShin:
+	gtkwave ./tb/build/wave.vcd &
 
 ef: 
 	sbt "test:runMain test.testModule"
@@ -282,17 +285,17 @@ VSimBack:
 
 
 
-tb:
+# tb:
-	iverilog -Wall \
+# 	iverilog -Wall \
-	-o ./build/wave.iverilog  \
+# 	-o ./build/wave.iverilog  \
-	-y ./tb  \
+# 	-y ./tb  \
-	-y ./generated/cdr/  \
+# 	-y ./generated/cdr/  \
-	-I ./tb  \
+# 	-I ./tb  \
-	-I ./generated/cdr/  \
+# 	-I ./generated/cdr/  \
-	-D RANDOMIZE_REG_INIT \
+# 	-D RANDOMIZE_REG_INIT \
-	./tb/backSys_tb.v 
+# 	./tb/backSys_tb.v 
-	vvp  -N ./build/wave.iverilog -lxt2
+# 	vvp  -N ./build/wave.iverilog -lxt2
 
-vcd:
+# vcd:
-	gtkwave ./build/wave.vcd &
+# 	gtkwave ./build/wave.vcd &
 

src/main/scala/backBoard/shin/SlaveParser.scala

@@ -118,7 +118,7 @@ abstract class SlaveParserBase extends Module{
   // val probeFrame: FrameHeader //固定化探针内容
 
   downSendGen.io.frameReq.valid :=
-    isDownSendPend //| 下行转发
+    isDownSendPend & downRecParser.io.subMsgReq.fire //| 下行转发
     //isDownSendProbe  //下行探针
 
   // assert( OneHot(isDownSendPend, isDownSendProbe) )
@@ -132,7 +132,7 @@ abstract class SlaveParserBase extends Module{
 
 
   upSendGen.io.frameReq.valid :=
-    isUpSendPend //|     上行转发
+    isUpSendPend & upRecParser.io.subMsgReq.fire //|     上行转发
     //isUpSendProbe |   // 上行探针
 
   // assert( OneHot(isUpSendPend, isUpSendProbe) )
@@ -165,8 +165,8 @@ abstract class SlaveParserBase extends Module{
 
 
 
-  val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } //子报文负载
+  val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 16)) } //子报文负载
-  val upRecFifo   = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
+  val upRecFifo   = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 16)) }
 
   val isDownRecPing = RegInit(false.B)
   val isUpRecPing   = RegInit(false.B)
@@ -210,7 +210,7 @@ abstract class SlaveParserBase extends Module{
 
 
 
-  when( isDownRecPing ){
+  when( ~isDownRecPing ){ //req fire 后 已经反相
     downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
     downRecFifo(0).io.enq.bits  := downRecParser.io.data.bits
     downRecParser.io.data.ready := downRecFifo(0).io.enq.ready
@@ -244,9 +244,9 @@ abstract class SlaveParserBase extends Module{
 
   io.sram_w.enr := false.B
 
-  io.sram_w.enw := 
+  io.sram_w.enw := //req fire 后 已经反相
-    ( isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
+    ( ~isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
-    (~isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
+    (  isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
   
 
 
@@ -290,7 +290,7 @@ abstract class SlaveParserBase extends Module{
     }
   }
 
-  when( isUpRecPing ){
+  when( ~isUpRecPing ){ //req fire 后 已经反相
     upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(0).io.enq.bits  := 
       Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U),
@@ -356,8 +356,8 @@ abstract class SlaveParserBase extends Module{
       isDownSubMsgValid(1) := false.B
     }
   } .elsewhen( downRecParser.io.subMsgReq.fire ){
-    when( isDownRecPing ){
     isDownRecPing := ~isDownRecPing
+    when( isDownRecPing ){
       assert( ~isDownSubMsgValid(0) )
       isDownSubMsgValid(0) := true.B
     } .otherwise{

src/main/scala/backBoard/shin/SlaveRecParser.scala

@@ -42,7 +42,7 @@ class SlaveRecParser extends Module{
   val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
 
   io.isError := stateCurr === STATE_ERROR
-  io.rec.ready := true.B
+  io.rec.ready := stateCurr =/= STATE_IDLE
   
   crc.io.isEnable :=
     stateCurr === STATE_HEADER |
@@ -84,10 +84,20 @@ class SlaveRecParser extends Module{
 
 
   io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE)
-  val frameHeader = Reg(new FrameHeader); io.frameReq.bits := frameHeader
+  val frameHeader = Reg(new FrameHeader)
+  io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
+  io.frameReq.bits.frameStyle  := io.rec.bits.tdata(1,0)
 
   io.subMsgReq.valid := (stateCurr === STATE_PAYLOAD_WORKCNT) & (stateNext === STATE_PAYLOAD_DATA)
-  val subMsgHeader = Reg(new SubMsgHeader); io.subMsgReq.bits := subMsgHeader
+  val subMsgHeader = Reg(new SubMsgHeader)
+
+  io.subMsgReq.bits.devIndex := subMsgHeader.devIndex
+  io.subMsgReq.bits.style    := subMsgHeader.style
+  io.subMsgReq.bits.address  := subMsgHeader.address
+  io.subMsgReq.bits.operator := subMsgHeader.operator
+  io.subMsgReq.bits.length   := subMsgHeader.length
+  io.subMsgReq.bits.workCnt  := subMsgHeader.workCnt | io.rec.bits.tdata(7,0)
+
 
   when( stateCurr === STATE_IDLE ){
     lengthCnt := 0.U
@@ -111,7 +121,7 @@ class SlaveRecParser extends Module{
 
   io.data.valid := stateCurr === STATE_PAYLOAD_DATA
   io.data.bits  := io.rec.bits.tdata
-  assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was recected by fifo!" )
+  assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was rejected by fifo!" )
 
 
 
@@ -176,7 +186,7 @@ class SlaveRecParser extends Module{
         ),
       ( stateCurr === STATE_PAYLOAD_DATA        ) -> Mux( isShortRx, STATE_ERROR,
           Mux( lengthCnt === ( subMsgHeader.length - 1.U), 
-            Mux( frameLenCnt === frameHeader.frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
+            Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
           ), STATE_PAYLOAD_DATA )
         ),
       ( stateCurr === STATE_CRC                 ) -> 

src/main/scala/backBoard/shin/SlaveSendGen.scala

@@ -77,8 +77,7 @@ class SlaveSendGen extends Module{
     }
   }
 
-  io.frameReq.ready := true.B
+
-  io.subMsgReq.ready := true.B
 
   val lengthCnt   = Reg(UInt(12.W))
   val frameLenCnt = Reg(UInt(12.W))
@@ -101,17 +100,18 @@ class SlaveSendGen extends Module{
 
 
 
-
+  io.frameReq.ready := true.B
+  io.subMsgReq.ready := stateCurr =/= STATE_SUBMSG_HEADER & stateNext === STATE_SUBMSG_HEADER
 
 
 
   stateNext := Mux1H(Seq(
     (stateCurr === STATE_IDLE)          -> Mux( io.frameReq.fire, STATE_FRAME_HEADER, STATE_IDLE ),
     (stateCurr === STATE_FRAME_HEADER)  -> Mux( lengthCnt === (2-1).U, Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ), STATE_FRAME_HEADER),
-    (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (64-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER),
+    (stateCurr === STATE_SUBMSG_HEADER) -> Mux( lengthCnt === (8-1).U, STATE_SUBMSG_DATA, STATE_SUBMSG_HEADER),
     (stateCurr === STATE_SUBMSG_DATA)   ->
       Mux( lengthCnt === subMsgInfoSel.length-1.U,    //已经发送完成该子报文
-        Mux( frameLenCnt === frameInfo.frameLenAim, STATE_CRC, //主报文长度达到， 进CRC
+        Mux( frameLenCnt === frameInfo.frameLenAim -1.U, STATE_CRC, //主报文长度达到， 进CRC
           Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_ERROR ) ), //主报文长度未到，进下一个子报文
         STATE_SUBMSG_DATA
       ),
@@ -153,7 +153,11 @@ class SlaveSendGen extends Module{
     (subMsgInfoSel.source === 1.U) -> io.data(1).bits,
   ))
 
-  crc.io.dataIn := tdata_submsg_data
+  crc.io.dataIn := Mux1H(Seq(
+    (stateCurr === STATE_FRAME_HEADER)  -> tdata_frame_header,
+    (stateCurr === STATE_SUBMSG_HEADER) -> tdata_submsg_header,
+    (stateCurr === STATE_SUBMSG_DATA)   -> tdata_submsg_data,
+  ))
 
 
   val tdata_crc = Mux1H(Seq(

tb/shinTest/SlaveParserTb.v

@@ -11,33 +11,37 @@ module slaveParserTb(
 
 
 wire        io_downIn_ready;
-reg         io_downIn_valid;
+reg         io_downIn_valid = 0;
-reg  [7:0]  io_downIn_bits_tdata;
+reg  [7:0]  io_downIn_bits_tdata = 0;
-reg         io_downIn_bits_tlast;
+reg         io_downIn_bits_tlast = 0;
-reg         io_downIn_bits_tuser;
+reg         io_downIn_bits_tuser = 0;
-reg         io_downOut_ready;
+
+reg         io_downOut_ready = 1;
 wire        io_downOut_valid;
 wire [7:0]  io_downOut_bits_tdata;
 wire        io_downOut_bits_tlast;
 wire        io_downOut_bits_tuser;
+
 wire        io_upIn_ready;
-reg         io_upIn_valid;
+reg         io_upIn_valid = 0;
-reg  [7:0]  io_upIn_bits_tdata;
+reg  [7:0]  io_upIn_bits_tdata = 0;
-reg         io_upIn_bits_tlast;
+reg         io_upIn_bits_tlast = 0;
-reg         io_upIn_bits_tuser;
+reg         io_upIn_bits_tuser = 0;
-reg         io_upOut_ready;
+
+reg         io_upOut_ready = 1;
 wire        io_upOut_valid;
 wire [7:0]  io_upOut_bits_tdata;
 wire        io_upOut_bits_tlast;
 wire        io_upOut_bits_tuser;
+
 wire [14:0] io_sram_r_addr;
 wire [7:0]  io_sram_r_dataw;
-reg  [7:0]  io_sram_r_datar;
+reg  [7:0]  io_sram_r_datar = 0;
 wire        io_sram_r_enw;
 wire        io_sram_r_enr;
 wire [14:0] io_sram_w_addr;
 wire [7:0]  io_sram_w_dataw;
-reg  [7:0]  io_sram_w_datar;
+reg  [7:0]  io_sram_w_datar = 0;
 wire        io_sram_w_enw;
 wire        io_sram_w_enr;
 
@@ -45,7 +49,7 @@ wire        io_sram_w_enr;
 
 
 
-s_SlaveParser SlaveParser(
+SlaveParser s_SlaveParser (
   .clock(clock),
   .reset(reset),
   .io_downIn_ready(io_downIn_ready),
@@ -98,7 +102,7 @@ initial begin
 	#100
 	reset <= 0;
 
-	#160000
+#160000
 	$display("Time Out !!!");
 	$stop;
 end
@@ -109,9 +113,142 @@ end
 
 initial
 begin
-	$dumpfile("./build/wave.vcd"); //生成的vcd文件名称
+	$dumpfile("./tb/build/wave.vcd"); //生成的vcd文件名称
 	$dumpvars(0, slaveParserTb);//tb模块名称
 end
 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+reg [7:0] testDownData[0:1000];
+
+initial begin
+  testDownData[0] = 8'hde;
+  testDownData[1] = 8'h0e;
+end
+
+// reg [11:0] testDownDataCnt = 0;
+
+
+
+
+
+
+// always @(posedge clock) begin
+  
+// end
+
+
+initial begin
+  #1000
+    @(posedge clock) #3 
+    io_downIn_valid = 1;
+    io_downIn_bits_tdata = 8'h20;
+
+    @( io_downIn_valid & io_downIn_ready)
+
+    @(posedge clock) #3 
+    io_downIn_valid = 1;
+    io_downIn_bits_tdata = 8'h00; //heeader length 512
+
+
+
+
+
+    for( integer i = 0; i < 8; i = i + 1 ) begin
+
+      @(posedge clock) #3 
+      io_downIn_valid = 1;
+      io_downIn_bits_tdata = $random; 
+
+      @(posedge clock) #3 
+      io_downIn_valid = 1;
+      io_downIn_bits_tdata = $random;
+
+      @(posedge clock) #3 
+      io_downIn_valid = 1;
+      io_downIn_bits_tdata = $random;
+
+      @(posedge clock) #3 
+      io_downIn_valid = 1;
+      io_downIn_bits_tdata = $random;
+
+      @(posedge clock) #3 
+      io_downIn_valid = 1;
+      io_downIn_bits_tdata = 8'h0;
+
+      @(posedge clock) #3 
+      io_downIn_valid = 1;
+      io_downIn_bits_tdata = 8'd56;
+
+      @(posedge clock) #3 
+      io_downIn_valid = 1;
+      io_downIn_bits_tdata = $random;
+
+      @(posedge clock) #3 
+      io_downIn_valid = 1;
+      io_downIn_bits_tdata = $random;
+
+      for( integer j = 0; j < 64-8; j = j+ 1 )begin
+        @(posedge clock) #3 
+        io_downIn_valid = 1;
+        io_downIn_bits_tdata = 8'ha5; //heeader length 512
+      end
+    end
+
+    @(posedge clock) #3 
+    io_downIn_valid = 1;
+    io_downIn_bits_tdata = $random;
+    io_downIn_bits_tlast = 0;
+    io_downIn_bits_tuser = 0;
+
+    @(posedge clock) #3 
+    io_downIn_valid = 1;
+    io_downIn_bits_tdata = $random;
+    io_downIn_bits_tlast = 0;
+    io_downIn_bits_tuser = 0;
+
+    @(posedge clock) #3 
+    io_downIn_valid = 1;
+    io_downIn_bits_tdata = $random;
+    io_downIn_bits_tlast = 0;
+    io_downIn_bits_tuser = 0;
+
+    @(posedge clock) #3 
+    io_downIn_valid = 1;
+    io_downIn_bits_tdata = $random;
+    io_downIn_bits_tlast = 1;
+    io_downIn_bits_tuser = 0;
+
+    @(posedge clock) #3 
+    io_downIn_valid = 0;
+    io_downIn_bits_tlast = 0;
+end
+
+
+
+
+
+
+
+
 endmodule