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转发功能已经调通

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This commit is contained in:
Ruige Lee
2025-04-14 16:43:10 +08:00
parent 00a7b0fe6e
commit 4552cc05db
5 changed files with 203 additions and 49 deletions
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20
src/main/scala/backBoard/shin/SlaveParser.scala
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@@ -118,7 +118,7 @@ abstract class SlaveParserBase extends Module{
// val probeFrame: FrameHeader //固定化探针内容
downSendGen.io.frameReq.valid :=
isDownSendPend //| 下行转发
isDownSendPend & downRecParser.io.subMsgReq.fire //| 下行转发
//isDownSendProbe //下行探针
// assert( OneHot(isDownSendPend, isDownSendProbe) )
@@ -132,7 +132,7 @@ abstract class SlaveParserBase extends Module{
upSendGen.io.frameReq.valid :=
isUpSendPend //| 上行转发
isUpSendPend & upRecParser.io.subMsgReq.fire //| 上行转发
//isUpSendProbe | // 上行探针
// assert( OneHot(isUpSendPend, isUpSendProbe) )
@@ -165,8 +165,8 @@ abstract class SlaveParserBase extends Module{
val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) } //子报文负载
val upRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 8)) }
val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 16)) } //子报文负载
val upRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 16)) }
val isDownRecPing = RegInit(false.B)
val isUpRecPing = RegInit(false.B)
@@ -210,7 +210,7 @@ abstract class SlaveParserBase extends Module{
when( isDownRecPing ){
when( ~isDownRecPing ){ //req fire 后 已经反相
downRecFifo(0).io.enq.valid := downRecParser.io.data.valid
downRecFifo(0).io.enq.bits := downRecParser.io.data.bits
downRecParser.io.data.ready := downRecFifo(0).io.enq.ready
@@ -244,9 +244,9 @@ abstract class SlaveParserBase extends Module{
io.sram_w.enr := false.B
io.sram_w.enw :=
( isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
(~isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
io.sram_w.enw := //req fire 后 已经反相
( ~isDownRecPing & downSubMsgInfo(0).devIndex === localDevIndex & (downSubMsgInfo(0).operator === 1.U | downSubMsgInfo(0).operator === 3.U)) |
( isDownRecPing & downSubMsgInfo(1).devIndex === localDevIndex & (downSubMsgInfo(1).operator === 1.U | downSubMsgInfo(1).operator === 3.U))
@@ -290,7 +290,7 @@ abstract class SlaveParserBase extends Module{
}
}
when( isUpRecPing ){
when( ~isUpRecPing ){ //req fire 后 已经反相
upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
upRecFifo(0).io.enq.bits :=
Mux( upSubMsgInfo(0).devIndex === localDevIndex & (upSubMsgInfo(0).operator === 2.U | upSubMsgInfo(0).operator === 3.U),
@@ -356,8 +356,8 @@ abstract class SlaveParserBase extends Module{
isDownSubMsgValid(1) := false.B
}
} .elsewhen( downRecParser.io.subMsgReq.fire ){
isDownRecPing := ~isDownRecPing
when( isDownRecPing ){
isDownRecPing := ~isDownRecPing
assert( ~isDownSubMsgValid(0) )
isDownSubMsgValid(0) := true.B
} .otherwise{