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Revert "使用外部分频器，面积没有变化"

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This reverts commit bfa432a471.
This commit is contained in:
RuigeLee
2024-05-09 11:39:44 +08:00
parent bfa432a471
commit 451763301d
3 changed files with 14 additions and 49 deletions
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1
src/main/scala/backBoard/BackBoardSlv.scala
View File

@@ -12,7 +12,6 @@ class BackBoardSlvIO extends Bundle{
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val clk8us = Input(Bool())
val lvds_down_din = Input(Bool())
val lvds_down_dout = Output(Bool())

31
src/main/scala/backBoard/LocalRegisters.scala
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@@ -60,9 +60,8 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
}
val clk16us = withClockAndReset( io.clk8us.asClock, reset ){ Reg(Bool())}
withClockAndReset( io.clk8us.asClock, reset ){ clk16us := ~clk16us }
// val (usCounter, usTrigger) = Counter(Range(0, 10))
val (usCounter, usTrigger) = Counter(Range(0, 10))
}
@@ -72,13 +71,13 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
val flashCounter = RegInit( 0.U( 15.W ) )
val flashCounter = RegInit( 0.U( 19.W ) )
val flash2HZ = Reg(Bool())
val flash1HZ = Reg(Bool())
when( clk16us ){
when( flashCounter === 31249.U ){
when( usTrigger ){
when( flashCounter >= 500000.U ){
flashCounter := 0.U
flash2HZ := ~flash2HZ
when( flash2HZ ){
@@ -104,21 +103,20 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
trait BackBoardSlvIn16 { this: BackBoardSlvLocal =>
val inPin = Wire(UInt(16.W))
val flitCnt = RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) ))
val flitTrigger = Wire(Vec(9, Bool()))
val digitalFilter = for( i <- 0 until 2 ) yield { RegInit( 1.U(8.W) ) }
val digitalIn = for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) }
val flitCnt = withClockAndReset( io.clk8us.asClock, reset ){ RegInit(MixedVecInit(Seq( false.B, 0.U(4.W), false.B, false.B, false.B, false.B, false.B, false.B, false.B) )) }
val flitTrigger = withClockAndReset( io.clk8us.asClock, reset ){ Wire(Vec(9, Bool())) }
val digitalIn = withClockAndReset( io.clk8us.asClock, reset ){ for( i <- 0 until 2 ) yield { Reg( Vec(8, Bool()) ) } }
withClockAndReset( io.clk8us.asClock, reset ){
flitTrigger(0) := ~RegNext(flitTrigger(0))
flitTrigger(1) := clk16us
// flitTrigger(1) := flitCnt(1) === 15.U
// when( ~RegNext(usTrigger) & usTrigger ){
// flitCnt(1) := flitCnt(1) + 1.U
// }
flitTrigger(1) := flitCnt(1) === 15.U
when( ~RegNext(usTrigger) & usTrigger ){
flitCnt(1) := flitCnt(1) + 1.U
}
flitTrigger(2) := flitCnt(2)
when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
@@ -204,7 +202,6 @@ withClockAndReset( io.clk8us.asClock, reset ){
}
}
}
}
}

31
src/main/verilog/di16_top.v
View File

@@ -25,9 +25,6 @@ wire clk_400m_a;
wire clk_100m_a;
wire clk_50m_a;
wire clk_10m_a;
wire clk_2m_a;
wire clk_500k_a;
wire clk_8us_a;
wire lock_o;
wire reset_stop;
@@ -128,33 +125,6 @@ CLKDIV Inst5_CLKDIVC(
.CLKOUT (clk_10m_a)
);
defparam Inst6_CLKDIVC.DIV_MODE="5";
defparam Inst6_CLKDIVC.GSREN="false";
CLKDIV Inst6_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_10m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_2m_a)
);
defparam Inst7_CLKDIVC.DIV_MODE="4";
defparam Inst7_CLKDIVC.GSREN="false";
CLKDIV Inst7_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_2m_a),
.CALIB (1'b0 ),
.CLKOUT (clk_500k_a)
);
defparam Inst8_CLKDIVC.DIV_MODE="4";
defparam Inst8_CLKDIVC.GSREN="false";
CLKDIV Inst8_CLKDIVC(
.RESETN (~reset_calib),
.HCLKIN (clk_500k_a),
.CALIB (1'b0 ),
.CLKOUT (clk_8us_a)
);
DIn16 i_din16(
.reset(~rst_n),
.clock(clk_10m_a),
@@ -163,7 +133,6 @@ DIn16 i_din16(
.io_oser_fclk(clk_50m_a),
.io_ides_pclk(clk_100m_a),
.io_ides_fclk(clk_400m_a),
.io_clk8us(clk_8us_a),
.io_lvds_down_din(lvds_down_din),
.io_lvds_down_dout(lvds_down_dout),