From 8779d92790e5283ff39bef4f5c4c735793befdd5 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 21 May 2025 10:28:36 +0800 Subject: [PATCH 1/2] =?UTF-8?q?=E6=8B=86=E5=88=86=E8=AF=BB=E5=86=99?= =?UTF-8?q?=E8=AE=BF=E9=97=AE=E5=9C=B0=E5=9D=80=E7=BA=BF=EF=BC=8C=E4=BB=A5?= =?UTF-8?q?=E4=BC=98=E5=8C=96=E6=97=B6=E5=BA=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 215 +++++++++--------- .../scala/backBoard/shin/SlaveParser.scala | 9 +- .../scala/backBoard/shin/SpiInterface.scala | 31 ++- tb/shinTest/ShinTopSpiTb.v | 2 +- 4 files changed, 137 insertions(+), 120 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 3c835cb..dfe78a5 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -375,7 +375,8 @@ abstract class InterfaceBase extends Module{ //spi信号 - val addrSel = Wire(UInt(16.W)) + val addrr = Wire(UInt(16.W)) + val addrw = Wire(UInt(16.W)) val dataw = Wire( UInt(8.W) ) val datar = Wire( UInt(8.W) ) val isEnW = Wire(Bool()) @@ -398,10 +399,16 @@ trait InterfaceMCUop{ this: InterfaceBase => ( cReg.spiSel === 2.U ) -> oQSpi.io.isEnW, )) - addrSel := Mux1H(Seq( - ( cReg.spiSel === 0.U ) -> iQSpi.io.addrSel, - ( cReg.spiSel === 1.U ) -> oSpi.io.addrSel, - ( cReg.spiSel === 2.U ) -> oQSpi.io.addrSel, + addrr := Mux1H(Seq( + ( cReg.spiSel === 0.U ) -> iQSpi.io.addrr, + ( cReg.spiSel === 1.U ) -> oSpi.io.addrr, + ( cReg.spiSel === 2.U ) -> oQSpi.io.addrr, + )) + + addrw := Mux1H(Seq( + ( cReg.spiSel === 0.U ) -> iQSpi.io.addrw, + ( cReg.spiSel === 1.U ) -> oSpi.io.addrw, + ( cReg.spiSel === 2.U ) -> oQSpi.io.addrw, )) dataw := Mux1H(Seq( @@ -417,15 +424,15 @@ trait InterfaceMCUop{ this: InterfaceBase => )) datar := MuxCase( 0.U, Array( - ((addrSel & "hFF00".U) === "h0000".U) -> AcquireReg(addr = addrSel), - ((addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar, - ((addrSel & "hFF00".U) === "h1000".U) -> 0.U, - ((addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar, - ((addrSel & "hFF00".U) === "h2000".U) -> 0.U, - ((addrSel & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar, - ((addrSel & "hFF00".U) === "h3000".U) -> 0.U, - ((addrSel & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar, - ((addrSel & "hFF00".U) === "h4000".U) -> 0.U, + ((addrr & "hFF00".U) === "h0000".U) -> AcquireReg(addr = addrr), + ((addrr & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar, + ((addrr & "hFF00".U) === "h1000".U) -> 0.U, + ((addrr & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar, + ((addrr & "hFF00".U) === "h2000".U) -> 0.U, + ((addrr & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar, + ((addrr & "hFF00".U) === "h3000".U) -> 0.U, + ((addrr & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar, + ((addrr & "hFF00".U) === "h4000".U) -> 0.U, )) iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U) @@ -433,42 +440,42 @@ trait InterfaceMCUop{ this: InterfaceBase => oQSpi.io.datar := Mux(cReg.spiSel === 2.U, datar, 0.U) when( isEnW ){ - printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrSel) + printf(s"SPI/QSPI Write 0x%x, @0x%x\n", dataw, addrw) } when( isEnR ){ - printf(s"SPI/QSPI Readout 0x%x, @0x%x\n", datar, addrSel) + printf(s"SPI/QSPI Readout 0x%x, @0x%x\n", datar, addrr) } - cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h0".U & cReg.mstOrSlv === 0.U ) - cReg.hwVersion := RegEnable( dataw , 0.U, isEnW & addrSel === "h1".U & cReg.mstOrSlv === 0.U ) + cReg.mstOrSlv := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h0".U & cReg.mstOrSlv === 0.U ) + cReg.hwVersion := RegEnable( dataw , 0.U, isEnW & addrw === "h1".U & cReg.mstOrSlv === 0.U ) cReg.hwSerial := Cat( (0 until 6).map{ i => - RegEnable( dataw, 0.U, isEnW & addrSel === ("h2".U + i.U) & cReg.mstOrSlv === 0.U ) + RegEnable( dataw, 0.U, isEnW & addrw === ("h2".U + i.U) & cReg.mstOrSlv === 0.U ) }.reverse ) - cReg.busRate := RegEnable( dataw, 0.U, isEnW & addrSel === "h8".U & cReg.mstOrSlv === 0.U ) - cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrSel === "h9".U & cReg.mstOrSlv === 0.U ) + cReg.busRate := RegEnable( dataw, 0.U, isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U ) + cReg.spiSel := RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U ) cReg.encryptKey := Cat( (0 until 16).map{ i => - RegEnable( dataw, 0.U, isEnW & addrSel === ("h50".U + i.U) & cReg.mstOrSlv === 0.U ) + RegEnable( dataw, 0.U, isEnW & addrw === ("h50".U + i.U) & cReg.mstOrSlv === 0.U ) }.reverse ) - mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrSel === "h20".U ) - mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrSel === "h20".U ) - // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrSel === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrSel === "h21".U ) ) + mReg.txSM := RegEnable( dataw(2,1), 0.U, isEnW & addrw === "h20".U ) + mReg.rxSM := RegEnable( dataw(4,3), 0.U, isEnW & addrw === "h20".U ) + // mReg.txLength := Cat( RegEnable( dataw, 0.U, isEnW & addrw === "h22".U ), RegEnable( dataw, 0.U, isEnW & addrw === "h21".U ) ) ( 0 until 128 ).map{ i => - cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrSel === ("h180".U + i.U)) ) + cReg.custom(i) := RegEnable( dataw, 0.U, isEnW & (addrw === ("h180".U + i.U)) ) } @@ -476,60 +483,60 @@ trait InterfaceMCUop{ this: InterfaceBase => mReg.rplTimeStampTx := Cat( - RegEnable( dataw, 0.U, isEnW & addrSel === "h25".U ), - RegEnable( dataw, 0.U, isEnW & addrSel === "h24".U ) + RegEnable( dataw, 0.U, isEnW & addrw === "h25".U ), + RegEnable( dataw, 0.U, isEnW & addrw === "h24".U ) ) when( isEnW & isSlvMode ){ - when( addrSel === "h120".U ){ + when( addrw === "h120".U ){ syncCfg := dataw } for( i <- 0 until 4 ){ - when( io.lvds.addrSel === ("h122".U + (2*i).U)){ + when( io.lvds.addrw === ("h122".U + (2*i).U)){ syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) - } .elsewhen( io.lvds.addrSel === ("h123".U + (2*i).U) ){ + } .elsewhen( io.lvds.addrw === ("h123".U + (2*i).U) ){ syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) } } - when( addrSel === "h130".U ){ + when( addrw === "h130".U ){ syncPoint := Cat( syncPoint(63,8), dataw ) - } .elsewhen( addrSel === "h131".U ){ + } .elsewhen( addrw === "h131".U ){ syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) ) - } .elsewhen( addrSel === "h132".U ){ + } .elsewhen( addrw === "h132".U ){ syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) ) - } .elsewhen( addrSel === "h133".U ){ + } .elsewhen( addrw === "h133".U ){ syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) ) - } .elsewhen( addrSel === "h134".U ){ + } .elsewhen( addrw === "h134".U ){ syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) ) - } .elsewhen( addrSel === "h135".U ){ + } .elsewhen( addrw === "h135".U ){ syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) ) - } .elsewhen( addrSel === "h136".U ){ + } .elsewhen( addrw === "h136".U ){ syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) ) - } .elsewhen( addrSel === "h137".U ){ + } .elsewhen( addrw === "h137".U ){ syncPoint := Cat( dataw, syncPoint(55,0) ) } - .elsewhen( addrSel === "h138".U ){ + .elsewhen( addrw === "h138".U ){ syncPeroid := Cat( syncPeroid(31,8), dataw ) - } .elsewhen( addrSel === "h139".U ){ + } .elsewhen( addrw === "h139".U ){ syncPeroid := Cat( syncPeroid(31,16), dataw, syncPeroid(7,0) ) - } .elsewhen( addrSel === "h13a".U ){ + } .elsewhen( addrw === "h13a".U ){ syncPeroid := Cat( syncPeroid(31,24), dataw, syncPeroid(15,0) ) - } .elsewhen( addrSel === "h13b".U ){ + } .elsewhen( addrw === "h13b".U ){ syncPeroid := Cat( dataw, syncPeroid(23,0) ) } for( i <- 1 until 4 ){ - when( addrSel === ("h13c".U + (4*(i-1)).U) ){ + when( addrw === ("h13c".U + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,8), dataw ) - } .elsewhen( addrSel === ("h13d".U + (4*(i-1)).U) ){ + } .elsewhen( addrw === ("h13d".U + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,16), dataw, syncOffset(i)(7,0) ) - } .elsewhen( addrSel === ("h13e".U + (4*(i-1)).U) ){ + } .elsewhen( addrw === ("h13e".U + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,24), dataw, syncOffset(i)(15,0) ) - } .elsewhen( addrSel === ("h13f".U + (4*(i-1)).U) ){ + } .elsewhen( addrw === ("h13f".U + (4*(i-1)).U) ){ syncOffset(i) := Cat( dataw, syncOffset(i)(23,0) ) } } @@ -541,116 +548,110 @@ trait InterfaceMCUop{ this: InterfaceBase => trait InterfaceCheckSM{ this: InterfaceBase => val isEnW: Bool - val addrSel: UInt + val addrw: UInt val dataw: UInt val isEnR: Bool for( i <- 0 until 8 ){ cReg.smTrigLen(i) := Cat( - RegEnable( dataw, 0.U, isEnW & addrSel === ("h303".U + (i*4).U) ), - RegEnable( dataw, 0.U, isEnW & addrSel === ("h302".U + (i*4).U) ), + RegEnable( dataw, 0.U, isEnW & addrw === ("h303".U + (i*4).U) ), + RegEnable( dataw, 0.U, isEnW & addrw === ("h302".U + (i*4).U) ), ) } - io.sram_r(0).addrr := addrSel - io.sram_r(1).addrr := addrSel - io.sram_r(2).addrr := addrSel - io.sram_r(3).addrr := addrSel + io.sram_r(0).addrr := addrr + io.sram_r(1).addrr := addrr + io.sram_r(2).addrr := addrr + io.sram_r(3).addrr := addrr - io.sram_r(0).enr := isEnR & (( addrSel & "hF800".U ) === "h0800".U) - io.sram_r(1).enr := isEnR & (( addrSel & "hF800".U ) === "h1800".U) - io.sram_r(2).enr := isEnR & (( addrSel & "hF800".U ) === "h2800".U) - io.sram_r(3).enr := isEnR & (( addrSel & "hF800".U ) === "h3800".U) + io.sram_r(0).enr := isEnR & (( addrr & "hF800".U ) === "h0800".U) + io.sram_r(1).enr := isEnR & (( addrr & "hF800".U ) === "h1800".U) + io.sram_r(2).enr := isEnR & (( addrr & "hF800".U ) === "h2800".U) + io.sram_r(3).enr := isEnR & (( addrr & "hF800".U ) === "h3800".U) - io.sram_w(0).addrw := addrSel - io.sram_w(1).addrw := addrSel - io.sram_w(2).addrw := addrSel - io.sram_w(3).addrw := addrSel + io.sram_w(0).addrw := addrw + io.sram_w(1).addrw := addrw + io.sram_w(2).addrw := addrw + io.sram_w(3).addrw := addrw io.sram_w(0).dataw := dataw io.sram_w(1).dataw := dataw io.sram_w(2).dataw := dataw io.sram_w(3).dataw := dataw - io.sram_w(0).enw := isEnW & (( addrSel & "hF800".U ) === "h1000".U) - io.sram_w(1).enw := isEnW & (( addrSel & "hF800".U ) === "h2000".U) - io.sram_w(2).enw := isEnW & (( addrSel & "hF800".U ) === "h3000".U) - io.sram_w(3).enw := isEnW & (( addrSel & "hF800".U ) === "h4000".U) + io.sram_w(0).enw := isEnW & (( addrw & "hF800".U ) === "h1000".U) + io.sram_w(1).enw := isEnW & (( addrw & "hF800".U ) === "h2000".U) + io.sram_w(2).enw := isEnW & (( addrw & "hF800".U ) === "h3000".U) + io.sram_w(3).enw := isEnW & (( addrw & "hF800".U ) === "h4000".U) - io.dSMdeq(0) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(0) - 1.U) - io.dSMdeq(1) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(2) - 1.U) - io.dSMdeq(2) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(4) - 1.U) - io.dSMdeq(3) := isEnR & (( addrSel & "hF800".U ) === "h0800".U) & (addrSel(10,0) === cReg.smTrigLen(6) - 1.U) + io.dSMdeq(0) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(0) - 1.U) + io.dSMdeq(1) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(2) - 1.U) + io.dSMdeq(2) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(4) - 1.U) + io.dSMdeq(3) := isEnR & (( addrr & "hF800".U ) === "h0800".U) & (addrr(10,0) === cReg.smTrigLen(6) - 1.U) - io.uSMenq(0) := isEnW & (( addrSel & "hF800".U ) === "h1000".U) & (addrSel(10,0) === cReg.smTrigLen(1) - 1.U) - io.uSMenq(1) := isEnW & (( addrSel & "hF800".U ) === "h2000".U) & (addrSel(10,0) === cReg.smTrigLen(3) - 1.U) - io.uSMenq(2) := isEnW & (( addrSel & "hF800".U ) === "h3000".U) & (addrSel(10,0) === cReg.smTrigLen(5) - 1.U) - io.uSMenq(3) := isEnW & (( addrSel & "hF800".U ) === "h4000".U) & (addrSel(10,0) === cReg.smTrigLen(7) - 1.U) + io.uSMenq(0) := isEnW & (( addrw & "hF800".U ) === "h1000".U) & (addrw(10,0) === cReg.smTrigLen(1) - 1.U) + io.uSMenq(1) := isEnW & (( addrw & "hF800".U ) === "h2000".U) & (addrw(10,0) === cReg.smTrigLen(3) - 1.U) + io.uSMenq(2) := isEnW & (( addrw & "hF800".U ) === "h3000".U) & (addrw(10,0) === cReg.smTrigLen(5) - 1.U) + io.uSMenq(3) := isEnW & (( addrw & "hF800".U ) === "h4000".U) & (addrw(10,0) === cReg.smTrigLen(7) - 1.U) } trait InterfaceLVDSop{ this: InterfaceBase => - // io.lvds.addrSel = Output(UInt(16.W)) - // io.lvds.dataw = Output( UInt(8.W) ) - // io.lvds.datar = Input( UInt(8.W) ) - // io.lvds.isEnW = Output(Bool()) - // io.lvds.isEnR = Output(Bool()) - - io.lvds.datar := AcquireReg(addr = io.lvds.addrSel) + io.lvds.datar := AcquireReg(addr = io.lvds.addrr) when( io.lvds.isEnW & isSlvMode ){ - when( io.lvds.addrSel === "h120".U ){ + when( io.lvds.addrw === "h120".U ){ syncCfg := io.lvds.dataw } for( i <- 0 until 4 ){ - when( io.lvds.addrSel === ("h122".U + (2*i).U)){ + when( io.lvds.addrw === ("h122".U + (2*i).U)){ syncWidth(i) := Cat( syncWidth(i)(15,8), io.lvds.dataw ) - } .elsewhen( io.lvds.addrSel === ("h123".U + (2*i).U) ){ + } .elsewhen( io.lvds.addrw === ("h123".U + (2*i).U) ){ syncWidth(i) := Cat( io.lvds.dataw, syncWidth(i)(7,0) ) } } - .elsewhen( io.lvds.addrSel === "h130".U ){ + .elsewhen( io.lvds.addrw === "h130".U ){ syncPoint := Cat( syncPoint(63,8), io.lvds.dataw ) - } .elsewhen( io.lvds.addrSel === "h131".U ){ + } .elsewhen( io.lvds.addrw === "h131".U ){ syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) ) - } .elsewhen( io.lvds.addrSel === "h132".U ){ + } .elsewhen( io.lvds.addrw === "h132".U ){ syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) ) - } .elsewhen( io.lvds.addrSel === "h133".U ){ + } .elsewhen( io.lvds.addrw === "h133".U ){ syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) ) - } .elsewhen( io.lvds.addrSel === "h134".U ){ + } .elsewhen( io.lvds.addrw === "h134".U ){ syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) ) - } .elsewhen( io.lvds.addrSel === "h135".U ){ + } .elsewhen( io.lvds.addrw === "h135".U ){ syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) ) - } .elsewhen( io.lvds.addrSel === "h136".U ){ + } .elsewhen( io.lvds.addrw === "h136".U ){ syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) ) - } .elsewhen( io.lvds.addrSel === "h137".U ){ + } .elsewhen( io.lvds.addrw === "h137".U ){ syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) ) } - .elsewhen( io.lvds.addrSel === "h138".U ){ + .elsewhen( io.lvds.addrw === "h138".U ){ syncPeroid := Cat( syncPeroid(31,8), io.lvds.dataw ) - } .elsewhen( io.lvds.addrSel === "h139".U ){ + } .elsewhen( io.lvds.addrw === "h139".U ){ syncPeroid := Cat( syncPeroid(31,16), io.lvds.dataw, syncPeroid(7,0) ) - } .elsewhen( io.lvds.addrSel === "h13a".U ){ + } .elsewhen( io.lvds.addrw === "h13a".U ){ syncPeroid := Cat( syncPeroid(31,24), io.lvds.dataw, syncPeroid(15,0) ) - } .elsewhen( io.lvds.addrSel === "h13b".U ){ + } .elsewhen( io.lvds.addrw === "h13b".U ){ syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) ) } for( i <- 1 until 4 ){ - when( io.lvds.addrSel === ("h13c".U + (4*(i-1)).U) ){ + when( io.lvds.addrw === ("h13c".U + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw ) - } .elsewhen( io.lvds.addrSel === ("h13d".U + (4*(i-1)).U) ){ + } .elsewhen( io.lvds.addrw === ("h13d".U + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,16), io.lvds.dataw, syncOffset(i)(7,0) ) - } .elsewhen( io.lvds.addrSel === ("h13e".U + (4*(i-1)).U) ){ + } .elsewhen( io.lvds.addrw === ("h13e".U + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,24), io.lvds.dataw, syncOffset(i)(15,0) ) - } .elsewhen( io.lvds.addrSel === ("h13f".U + (4*(i-1)).U) ){ + } .elsewhen( io.lvds.addrw === ("h13f".U + (4*(i-1)).U) ){ syncOffset(i) := Cat( io.lvds.dataw, syncOffset(i)(23,0) ) } } @@ -662,10 +663,10 @@ trait InterfaceSync{ this: InterfaceBase => cReg.mstDeltaTime := io.mstDeltaTime // Cat( - //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d3".U ), - //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d2".U ), - //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d1".U ), - //RegEnable( dataw, 0.U, isEnW & addrSel === "h1d0".U ), + //RegEnable( dataw, 0.U, isEnW & addrw === "h1d3".U ), + //RegEnable( dataw, 0.U, isEnW & addrw === "h1d2".U ), + //RegEnable( dataw, 0.U, isEnW & addrw === "h1d1".U ), + //RegEnable( dataw, 0.U, isEnW & addrw === "h1d0".U ), // ) // sReg.mstTimeStamp := io.mstTimeStamp @@ -683,7 +684,7 @@ trait InterfaceSync{ this: InterfaceBase => syncPoint := syncPoint + cReg.syncPeroid } .elsewhen( ~sReg.syncCfg(4+0) & syncResetCnt(0) === sReg.syncWidth(0) ){ syncSign(0) := false.B - } .elsewhen( sReg.syncCfg(4+0) & isEnW & addrSel === "h122".U ){ + } .elsewhen( sReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){ syncSign(0) := false.B } @@ -699,7 +700,7 @@ trait InterfaceSync{ this: InterfaceBase => syncSign(i) := true.B } .elsewhen( ~sReg.syncCfg(4+i) & syncResetCnt(i) === sReg.syncWidth(i) ){ syncSign(i) := false.B - } .elsewhen( sReg.syncCfg(4+i) & isEnW & addrSel === ("h122".U + (2*i).U) ){ + } .elsewhen( sReg.syncCfg(4+i) & isEnW & addrw === ("h122".U + (2*i).U) ){ syncSign(i) := false.B } @@ -737,7 +738,7 @@ with InterfaceSync io.txReq.bits.txSM := mReg.txSM io.txReq.bits.rxSM := mReg.rxSM // io.txReq.bits.txLength := //mReg.txLength - io.txReq.valid := isEnW & addrSel === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U + io.txReq.valid := isEnW & addrw === "h20".U & dataw.extract(0) === "b1".U //& mReg.txLength =/= 0.U diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala index 61e6bf6..7b4ce19 100644 --- a/src/main/scala/backBoard/shin/SlaveParser.scala +++ b/src/main/scala/backBoard/shin/SlaveParser.scala @@ -537,10 +537,11 @@ trait SlaveParserRW{ this: SlaveParserBase => - io.lvds.addrSel := Mux1H(Seq( - isRead -> addrr(10,0), - isWrite -> addrw(10,0), - )) + + io.lvds.addrr := addrr(10,0) + io.lvds.addrw := addrw(10,0) + + assert( ~(isRead & isWrite) ) diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala index 7945590..d7d9b61 100644 --- a/src/main/scala/backBoard/shin/SpiInterface.scala +++ b/src/main/scala/backBoard/shin/SpiInterface.scala @@ -20,7 +20,8 @@ class SSPIInterfaceIO extends Bundle{ } class RegAccessInterfaceIO extends Bundle{ - val addrSel = Output(UInt(16.W)) + val addrw = Output(UInt(16.W)) + val addrr = Output(UInt(16.W)) val dataw = Output( UInt(8.W) ) val datar = Input( UInt(8.W) ) val isEnW = Output(Bool()) @@ -50,7 +51,8 @@ abstract class SpiInterfaceBase extends Module{ - val addrSel = Reg(UInt(16.W)) + val addrw = Reg(UInt(16.W)) + val addrr = Reg(UInt(16.W)) val spiCmd = Reg(UInt(8.W)) val isSpiWrite = spiCmd === 0.U @@ -65,8 +67,10 @@ abstract class SpiInterfaceBase extends Module{ (isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U) io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & isSpiWrite & byteSel >= 4.U io.dataw := exRegi - io.addrSel := - Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况 + io.addrr := Mux( isSpiRead, addrr + 1.U, addrr ) + io.addrw := addrw + // io.addrSel := + // Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况 val readData = RegEnable(io.datar, io.isEnR) @@ -81,17 +85,28 @@ abstract class SpiInterfaceBase extends Module{ when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 - addrSel := 0.U + addrw := 0.U } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte - addrSel := exRegi + addrw := exRegi } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte - addrSel := Cat(exRegi, addrSel(7,0)) + addrw := Cat(exRegi, addrw(7,0)) } .otherwise{ // byteSel > 1.U when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){ - addrSel := addrSel + 1.U + addrw := addrw + 1.U } } + when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 + addrr := 0.U + } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte + addrr := exRegi + } .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte + addrr := Cat(exRegi, addrr(7,0)) + } .otherwise{ // byteSel > 1.U + when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){ + addrr := addrr + 1.U + } + } when( shiftCSn(2) & ~shiftCSn(1) ){ //CS下跳 spiCmd := "hFF".U diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 1eed35b..82d0423 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -628,7 +628,7 @@ initial begin $fdisplay(spidata_file, "--->>>嗅探"); //设置SM1在写入0x3地址触发enq - txBuf[0+3] = 8'h03; + txBuf[0+3] = 8'h04; txBuf[1+3] = 8'h00; spi_trans( (16'h0302), (`SPI_WRITE), (2), (`IF_IDX(0)) ); spi_trans( (16'h0306), (`SPI_WRITE), (2), (`IF_IDX(0)) ); From f8712482eeec5fa3274d47eb7ce21044f59785e3 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 21 May 2025 10:48:22 +0800 Subject: [PATCH 2/2] =?UTF-8?q?=E4=BF=AE=E5=A4=8D=E8=AE=BF=E9=97=AE?= =?UTF-8?q?=E5=AF=84=E5=AD=98=E5=99=A8=E7=A9=BA=E9=97=B4=E8=8C=83=E5=9B=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index dfe78a5..f1a3388 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -424,15 +424,15 @@ trait InterfaceMCUop{ this: InterfaceBase => )) datar := MuxCase( 0.U, Array( - ((addrr & "hFF00".U) === "h0000".U) -> AcquireReg(addr = addrr), - ((addrr & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar, - ((addrr & "hFF00".U) === "h1000".U) -> 0.U, - ((addrr & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar, - ((addrr & "hFF00".U) === "h2000".U) -> 0.U, - ((addrr & "hFF00".U) === "h2800".U) -> io.sram_r(2).datar, - ((addrr & "hFF00".U) === "h3000".U) -> 0.U, - ((addrr & "hFF00".U) === "h3800".U) -> io.sram_r(3).datar, - ((addrr & "hFF00".U) === "h4000".U) -> 0.U, + ((addrr & "hF800".U) === "h0000".U) -> AcquireReg(addr = addrr), + ((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar, + ((addrr & "hF800".U) === "h1000".U) -> 0.U, + ((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar, + ((addrr & "hF800".U) === "h2000".U) -> 0.U, + ((addrr & "hF800".U) === "h2800".U) -> io.sram_r(2).datar, + ((addrr & "hF800".U) === "h3000".U) -> 0.U, + ((addrr & "hF800".U) === "h3800".U) -> io.sram_r(3).datar, + ((addrr & "hF800".U) === "h4000".U) -> 0.U, )) iQSpi.io.datar := Mux(cReg.spiSel === 0.U, datar, 0.U)