From 4285882a7abccf9b8c3b1e175f51cb78977986e0 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 8 Nov 2023 16:06:26 +0800 Subject: [PATCH] =?UTF-8?q?=E5=B9=BF=E6=92=AD=E8=B7=AF=E5=BE=84=E5=BE=88?= =?UTF-8?q?=E5=A5=BD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/Switch/Robin.scala | 7 +++++-- src/main/scala/Switch/Switch.scala | 4 +++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/main/scala/Switch/Robin.scala b/src/main/scala/Switch/Robin.scala index 4c55595..fef75d4 100644 --- a/src/main/scala/Switch/Robin.scala +++ b/src/main/scala/Switch/Robin.scala @@ -12,15 +12,17 @@ import freechips.rocketchip.tilelink._ import MAC._ -class Robin_Bundle extends Bundle{ +class Robin_Bundle(implicit p: Parameters) extends SwitchBundle{ val rx = Decoupled(new Mac_Stream_Bundle) val mInfo = new Rx_MuxInfo_Bundle + } class Robin(implicit p: Parameters) extends SwitchModule{ class RobinIO extends Bundle{ val enq = Vec( chn+1, Flipped(new Robin_Bundle) ) - val deq = new Robin_Bundle + val deq = new Robin_Bundle + val sel = Output(UInt( (log2Ceil(chn+1)).W )) } val io: RobinIO = IO(new RobinIO) @@ -30,6 +32,7 @@ class Robin(implicit p: Parameters) extends SwitchModule{ val isLock = RegInit(false.B) val lockChn = Reg(UInt((log2Ceil(chn+1)).W)) + io.sel := lockChn val lfsr = ~LFSR( log2Ceil(chn+1), ~isLock) diff --git a/src/main/scala/Switch/Switch.scala b/src/main/scala/Switch/Switch.scala index 9d56cea..df0fed3 100644 --- a/src/main/scala/Switch/Switch.scala +++ b/src/main/scala/Switch/Switch.scala @@ -152,8 +152,10 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out robin.io.deq.rx.ready := tempTxPort(destChn).ready } .otherwise{ for( i <- 0 until chn+1 ){ + when( i.U =/= robin.io.sel ){ tempTxPort(i).valid := robin.io.deq.rx.valid & allTxReady - tempTxPort(i).bits := robin.io.deq.rx.bits + tempTxPort(i).bits := robin.io.deq.rx.bits + } } robin.io.deq.rx.ready := allTxReady }