diff --git a/src/main/scala/Switch/Robin.scala b/src/main/scala/Switch/Robin.scala
index 4c55595..fef75d4 100644
--- a/src/main/scala/Switch/Robin.scala
+++ b/src/main/scala/Switch/Robin.scala
@@ -12,15 +12,17 @@ import freechips.rocketchip.tilelink._
 
 import MAC._
 
-class Robin_Bundle extends Bundle{
+class Robin_Bundle(implicit p: Parameters) extends SwitchBundle{
   val rx = Decoupled(new Mac_Stream_Bundle)
   val mInfo = new Rx_MuxInfo_Bundle
+
 }
 
 class Robin(implicit p: Parameters) extends SwitchModule{
   class RobinIO extends Bundle{
     val enq = Vec( chn+1, Flipped(new Robin_Bundle) )
-    val deq = new Robin_Bundle    
+    val deq = new Robin_Bundle
+    val sel = Output(UInt( (log2Ceil(chn+1)).W ))
   }
 
   val io: RobinIO = IO(new RobinIO)
@@ -30,6 +32,7 @@ class Robin(implicit p: Parameters) extends SwitchModule{
 
   val isLock = RegInit(false.B)
   val lockChn = Reg(UInt((log2Ceil(chn+1)).W))
+  io.sel := lockChn
 
   val lfsr = ~LFSR( log2Ceil(chn+1), ~isLock)
 
diff --git a/src/main/scala/Switch/Switch.scala b/src/main/scala/Switch/Switch.scala
index 9d56cea..df0fed3 100644
--- a/src/main/scala/Switch/Switch.scala
+++ b/src/main/scala/Switch/Switch.scala
@@ -152,8 +152,10 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
       robin.io.deq.rx.ready := tempTxPort(destChn).ready
     } .otherwise{
       for( i <- 0 until chn+1 ){
+        when( i.U =/= robin.io.sel ){
         tempTxPort(i).valid := robin.io.deq.rx.valid & allTxReady
-        tempTxPort(i).bits  := robin.io.deq.rx.bits
+        tempTxPort(i).bits  := robin.io.deq.rx.bits          
+        }
       }
       robin.io.deq.rx.ready := allTxReady
     }