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增加5选3多数表决滤波

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RuigeLee
2025-08-09 22:22:19 +08:00
parent fca32f0996
commit 424e07a076
1 changed files with 25 additions and 13 deletions
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38
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -78,21 +78,33 @@ trait CDRInMultiSample{ this: CDRInBase =>
}
val flitReg = for( i <- 0 until 16 ) yield {
if( i == 0 ) {
(sampleReg(15) & sampleReg(0)) |
(sampleReg(15) & sampleReg(1)) |
(sampleReg(0) & sampleReg(1))
} else if ( i > 0 && i < 15 ){
(sampleReg(i-1) & sampleReg(i)) |
(sampleReg(i-1) & sampleReg(i+1)) |
(sampleReg(i) & sampleReg(i+1))
} else// ( i == 15 )
(sampleReg(14) & sampleReg(15)) |
(sampleReg(14) & sampleReg(0)) |
(sampleReg(15) & sampleReg(0))
val flitReg =
if(false){
for( i <- 0 until 16 ) yield {
sampleReg(i)
}
} else if (true){ //5选3 多数投票 滤波
for( i <- 0 until 16 ) yield {
(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i-1+16)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i+0)%16) & sampleReg((i+1)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i+0)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-2+16)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-1+16)%16) & sampleReg((i+0)%16) & sampleReg((i+1)%16)) |
(sampleReg((i-1+16)%16) & sampleReg((i+0)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-1+16)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16)) |
(sampleReg((i-0)%16) & sampleReg((i+1)%16) & sampleReg((i+2)%16))
}
} else { //3选2 多数投票 滤波
for( i <- 0 until 16 ) yield {
(sampleReg((i-1+16)%16) & sampleReg((i+0)%16)) |
(sampleReg((i-1+16)%16) & sampleReg((i+1)%16)) |
(sampleReg((i+0)%16) & sampleReg((i+1)%16))
}
}
val arbLock = Reg(UInt( 16.W ))
//优先级电路，优先选择跳变的后一相进行操作，电路上需要做成可调的