From 41f0b5b0574cd54273c2d9853424d64636a1edce Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Fri, 23 May 2025 17:22:59 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=B8=AD=E6=96=AD?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 65 +++++++++++++++++-- src/main/scala/backBoard/shin/ShinTop.scala | 27 ++++++++ tb/shinTest/ShinTopSpiTb.v | 15 +++-- 3 files changed, 98 insertions(+), 9 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 5964751..d20df1b 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -16,6 +16,10 @@ class CommonRegisterBundle extends Bundle{ val encryptKey = UInt(128.W) val isEncrypt = Bool() + val intEnable = UInt(16.W) + val intStatus = UInt(16.W) + + // val upRecErrorCnt = UInt(32.W) // val downRecErrorCnt = UInt(32.W) // val upForwardErrorCnt = UInt(32.W) @@ -58,10 +62,6 @@ class MasterRegisterBundle extends Bundle{ val rplTimeStampTx = UInt(16.W) - // val intEnable = UInt(8.W) - // val intMask = UInt(8.W) - // val intStatus = UInt(8.W) - } @@ -171,6 +171,10 @@ class InterfaceIO extends Bundle{ val initEncryptor = Valid(UInt(128.W)) val isSoftReset = Output(Bool()) + val intMstTrig = Input(Vec(2, Bool())) + val intSlvTrig = Input(Vec(8, Bool())) + + val interrupt = Output(Bool()) } @@ -249,6 +253,10 @@ abstract class InterfaceBase extends Module{ Seq( (addr === "h60".U ) -> cReg.isEncrypt, + (addr === "h70".U ) -> cReg.intEnable(7,0), + (addr === "h71".U ) -> cReg.intEnable(15,8), + (addr === "h72".U ) -> cReg.intStatus(7,0), + (addr === "h73".U ) -> cReg.intStatus(15,8), (addr === "hc0".U ) -> Cat( sReg.isDevOnRightModify, sReg.isDevOnRight, 0.U(3.W) ), (addr === "hc2".U ) -> sReg.indexOfRightDev(7,0), (addr === "hc3".U ) -> sReg.indexOfRightDev(13,8), @@ -728,6 +736,55 @@ trait InterfaceSync{ this: InterfaceBase => trait InterfaceSystem{ this: InterfaceBase => io.isSoftReset := ShiftRegister( isEnW & addrw === "h40".U, 16, false.B, true.B ) + + cReg.intEnable := + Cat( + RegEnable( dataw, 0.U, isEnW & addrw === "h71".U ), + RegEnable( dataw, 0.U, isEnW & addrw === "h70".U ) + ) + + val intStatus = for( _ <- 0 until 16 ) yield { RegInit(false.B) } + cReg.intStatus := Cat( intStatus.reverse ) + + val intMstTrig = Input(Vec(2, Bool())) + val intSlvTrig = Input(Vec(8, Bool())) + + //主站发送完成 + when( io.intMstTrig(0) ){ + intStatus(0) := true.B + } + + //主站接收完成 + when( io.intMstTrig(1) ){ + intStatus(1) := true.B + } + + //主站发送周期到了 + + + //主站接收看门狗溢出 + + + //从站SM请求 + for( i <- 0 until 8 ){ + when( io.intSlvTrig(i) ){ + intStatus(8+i) := true.B + } + } + + + + for( i <- 0 until 8 ){ + when( dataw.extract(i) & isEnW & addrw === "h74".U ){ + intStatus(i) := false.B + } + when( dataw.extract(i) & isEnW & addrw === "h75".U ){ + intStatus(i+8) := false.B + } + } + + io.interrupt := intStatus.reduce(_|_) + } class Interface extends InterfaceBase diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index e35412d..160959f 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -46,6 +46,8 @@ class ShinTopIO extends Bundle{ val isSoftReset = Output(Bool()) val ledTest = Output(UInt(8.W)) + + val interrupt = Output(Bool()) } @@ -74,6 +76,7 @@ abstract class ShinTopBase extends Module{ io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U ) io.isSoftReset := interface.io.isSoftReset + io.interrupt := interface.io.interrupt downCDRIn.io.serDat := io.dDatIn downCDRIn.io.overCLK := io.clk8x @@ -238,6 +241,17 @@ abstract class ShinTopBase extends Module{ interface.io.slvDeltaTime := 0.U interface.io.deltaFinal := 0.U + interface.io.intMstTrig(0) := false.B + interface.io.intMstTrig(1) := false.B + + interface.io.intSlvTrig(0) := false.B + interface.io.intSlvTrig(1) := false.B + interface.io.intSlvTrig(2) := false.B + interface.io.intSlvTrig(3) := false.B + interface.io.intSlvTrig(4) := false.B + interface.io.intSlvTrig(5) := false.B + interface.io.intSlvTrig(6) := false.B + interface.io.intSlvTrig(7) := false.B } @@ -285,6 +299,9 @@ trait ShinTopMaster{ this: ShinTopBase => interface.io.mstDeltaTime := masterParser.io.deltaTimeStamp + interface.io.intMstTrig(0) := masterParser.io.txDeq + interface.io.intMstTrig(1) := masterParser.io.rxEnq + } masterParser.io.req := interface.io.txReq.valid @@ -335,6 +352,16 @@ trait ShinTopSlave{ this: ShinTopBase => interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime interface.io.deltaFinal := slaveParser.io.deltaFinal + + interface.io.intSlvTrig(0) := slaveParser.io.dSMenq(0) + interface.io.intSlvTrig(1) := slaveParser.io.uSMdeq(0) + interface.io.intSlvTrig(2) := slaveParser.io.dSMenq(1) + interface.io.intSlvTrig(3) := slaveParser.io.uSMdeq(1) + interface.io.intSlvTrig(4) := slaveParser.io.dSMenq(2) + interface.io.intSlvTrig(5) := slaveParser.io.uSMdeq(2) + interface.io.intSlvTrig(6) := slaveParser.io.dSMenq(3) + interface.io.intSlvTrig(7) := slaveParser.io.uSMdeq(3) + } interface.io.lvds <> slaveParser.io.lvds diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index a76793d..cb61157 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -70,7 +70,8 @@ ShinTop s_ShinTop_Mst( .io_rsp_valid(isResp), .io_rsp_bits_isError(), - .io_isSoftReset(isSoftReset[0]) + .io_isSoftReset(isSoftReset[0]), + .io_interrupt() ); ShinTop s_ShinTop_slv0( @@ -102,7 +103,8 @@ ShinTop s_ShinTop_slv0( .io_rsp_valid(), .io_rsp_bits_isError(), - .io_isSoftReset(isSoftReset[1]) + .io_isSoftReset(isSoftReset[1]), + .io_interrupt() ); ShinTop s_ShinTop_slv1( @@ -134,7 +136,8 @@ ShinTop s_ShinTop_slv1( .io_rsp_valid(), .io_rsp_bits_isError(), - .io_isSoftReset(isSoftReset[2]) + .io_isSoftReset(isSoftReset[2]), + .io_interrupt() ); ShinTop s_ShinTop_slv2( @@ -166,7 +169,8 @@ ShinTop s_ShinTop_slv2( .io_rsp_valid(), .io_rsp_bits_isError(), - .io_isSoftReset(isSoftReset[3]) + .io_isSoftReset(isSoftReset[3]), + .io_interrupt() ); ShinTop s_ShinTop_slv3( @@ -198,7 +202,8 @@ ShinTop s_ShinTop_slv3( .io_rsp_valid(), .io_rsp_bits_isError(), - .io_isSoftReset(isSoftReset[4]) + .io_isSoftReset(isSoftReset[4]), + .io_interrupt() );