diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index 220265b..bb70219 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -73,7 +73,7 @@ class CommonRegisterBundle extends Bundle{
 
   val wdtStatus = UInt(32.W)
   val wdtEnable = UInt(32.W)
-  val wdtTarCnt = Vec( 17, UInt(32.W) )
+  val wdtTarCnt = Vec( 18, UInt(32.W) )
 
   val timeStamp = UInt(64.W)
   val mstDeltaTime = UInt(32.W)
@@ -181,7 +181,7 @@ class InterfaceIO extends Bundle{
 
   val interrupt = Output(Bool())
 
-  val wdtTrigger = Input(Vec(17, Bool()))
+  val wdtTrigger = Input(Vec(18, Bool()))
 
   val downRecStat = Input(new Stat_IO_Bundle)
   val upRecStat   = Input(new Stat_IO_Bundle)
@@ -670,7 +670,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   }
 
 
-  val wdtStatus = for( i <- 0 until 17 ) yield { RegInit(false.B) }
+  val wdtStatus = for( i <- 0 until 18 ) yield { RegInit(false.B) } //1+16+1
   cReg.wdtStatus := Cat( wdtStatus.reverse )
 
   for( i <- 0 until 8 ){
@@ -685,7 +685,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
       wdtStatus(8+i) := true.B
     }
   }
-  for( i <- 0 until 1 ){
+  for( i <- 0 until 2 ){
     when( isEnW & addrw === "h402".U & dataw.extract(i) ){
       wdtStatus(16+i) := false.B
     } .elsewhen(io.wdtTrigger(16+i) & cReg.wdtEnable.extract(16+i)){
@@ -695,12 +695,12 @@ trait InterfaceMCUop{ this: InterfaceBase =>
 
   cReg.wdtEnable := 
     Cat(
-      RegEnable( dataw.extract(0), 0.U, isEnW & addrw === "h406".U ),
+      RegEnable( dataw(1,0), 0.U, isEnW & addrw === "h406".U ),
       RegEnable( dataw,            0.U, isEnW & addrw === "h405".U ),
       RegEnable( dataw,            0.U, isEnW & addrw === "h404".U ),
     )
 
-  for( i <- 0 until 17 ){
+  for( i <- 0 until 18 ){
     cReg.wdtTarCnt(i) :=
       Cat(
         RegEnable( dataw, 0.U, isEnW & addrw === ( "h40b".U (16.W) + (4*i).U ) ),
@@ -989,7 +989,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
 
 
   //看门狗溢出
-  when( io.wdtTrigger.reduce(_|_) ){
+  val isWdtTrigAndEnable = (0 until 18).map{ i => (io.wdtTrigger(i) & cReg.wdtEnable(i))}.reduce(_|_)
+  when( isWdtTrigAndEnable ){
     intStatus(4) := true.B
   }
 
@@ -1046,7 +1047,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
     (io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成
     (io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成
     false.B | //主站发送周期到了
-    (~RegNext(io.wdtTrigger.reduce(_|_), false.B) & io.wdtTrigger.reduce(_|_) & cReg.intEnable(4)) | //主站接收看门狗溢出
+    (~RegNext(isWdtTrigAndEnable, false.B) & isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出
     (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求
     (0 until 4).map{ i => io.intTransEnd(i) & cReg.intEnable(16+i)}.reduce(_|_) | //传输完成请求 16,17,18,19
     io.intHWTrig(0) | //下行接收硬件错误
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 791a45f..6dba0b7 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -377,7 +377,7 @@ trait ShinTopSlave{ this: ShinTopBase =>
 
 trait ShinTopWatchDog{ this: ShinTopBase =>
 
-
+  //看门狗1~16，SM监控
   val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
   val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) }
 
@@ -407,27 +407,42 @@ trait ShinTopWatchDog{ this: ShinTopBase =>
     interface.io.wdtTrigger(i+1) := wdtSMCnt(i) === interface.io.cReg.wdtTarCnt(i+1)
   }
 
+  //看门狗0 发送后回包是否超时
+  val isWdtRec2RtnEnable = RegInit(false.B)
+  val wdtRec2RtnCnt = Reg(UInt(32.W))
 
-  val isWdtRecEnable = RegInit(false.B)
-  val wdtRecCnt = Reg(UInt(32.W))
-
-  when( upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast ){
-    isWdtRecEnable := false.B
-  } .elsewhen( ~isWdtRecEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
-    isWdtRecEnable := true.B
+  when( 
+    (upCDRIn.io.axis.fire & upCDRIn.io.axis.bits.tlast) |
+    ~interface.io.cReg.wdtEnable.extract(0)
+  ){
+    isWdtRec2RtnEnable := false.B
+  } .elsewhen( ~isWdtRec2RtnEnable & downCDROut.io.axis.fire & interface.io.cReg.wdtEnable.extract(0) ){
+    isWdtRec2RtnEnable := true.B
   }
 
-  when( isWdtRecEnable & (wdtRecCnt < interface.io.cReg.wdtTarCnt(0)) ){
-    wdtRecCnt := wdtRecCnt + 1.U
-  } .elsewhen( ~isWdtRecEnable ){
-    wdtRecCnt := 0.U
+  when( isWdtRec2RtnEnable & (wdtRec2RtnCnt < interface.io.cReg.wdtTarCnt(0)) ){
+    wdtRec2RtnCnt := wdtRec2RtnCnt + 1.U
+  } .elsewhen( ~isWdtRec2RtnEnable ){
+    wdtRec2RtnCnt := 0.U
   }
 
   // assert( wdtRecCnt < interface.io.cReg.wdtTarCnt(0), "Assert Failed! wdtRecCnt is larger than wdtTarCnt, Special situation?" )
 
-  interface.io.wdtTrigger(0) := wdtRecCnt === interface.io.cReg.wdtTarCnt(0)
+  interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0)
 
+  //看门狗17
+  val wdtRec2RecCnt = Reg(UInt(32.W))
 
+  when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
+    wdtRec2RecCnt := wdtRec2RecCnt + 1.U
+  } .elsewhen(
+    ~interface.io.cReg.wdtEnable.extract(17) |
+    downCDRIn.io.axis.fire
+  ){
+    wdtRec2RecCnt := 0.U
+  }
+
+  interface.io.wdtTrigger(17) := wdtRec2RecCnt === interface.io.cReg.wdtTarCnt(17)
 
 }