使用4b/5b加跳变时钟选择法升级CDR

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -14,6 +14,7 @@ class CDRInIO extends Bundle{
 
 abstract class CDRInBase extends Module{
   def sampleRate: Int = 4
+  require( sampleRate == 4 )
 
   val io: CDRInIO = IO(new CDRInIO)
 
@@ -23,25 +24,60 @@ abstract class CDRInBase extends Module{
 trait CDRInOverSample{ this: CDRInBase =>
   val sampleReg = withClockAndReset(io.overCLK.asClock, reset.asBool){ ShiftRegisters( RegNext(io.serDat), sampleRate ) }
 
-  val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
-  val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
-  val isArbLock = RegInit(false.B)
 
-  for( i <- 0 until sampleRate ){
-    arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
-    when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
-      isArbLock := true.B
-      arbSel := i.U
-    }
 
+  // val arbShiftData = for( i <- 0 until sampleRate ) yield { RegInit(0.U(24.W)) }
+  // val arbSel = Reg(UInt( log2Ceil(sampleRate).W ))
+  // val isArbLock = RegInit(false.B)
+
+  // for( i <- 0 until sampleRate ){
+  //   arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
+  //   when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
+  //     isArbLock := true.B
+  //     arbSel := i.U
+  //   }
+  // }
+
+  // when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
+  //   isArbLock := false.B
+  // }
+
+  // val syncSerDat = 
+  //   Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
+
+  val arbCnt  = withClockAndReset(io.overCLK.asClock, reset.asBool){ RegInit("b0001".U(sampleRate.W)); arbCnt := Cat( arbCnt << 1, arbCnt.extract(3) ) }
+  val arbLock = withClockAndReset(io.overCLK.asClock, reset.asBool){ Reg(UInt( sampleRate.W )) }
+  when( sampleReg(0) ^ sampleReg(1) ){
+    arbLock := arbCnt
   }
 
-  when( ( 0 until sampleRate ).map{ i => (arbShiftData(i) === 0.U) }.reduce(_&_) ){
+  val asyncSerDat = Mux1H(Seq(
-    isArbLock := false.B
+    (arbLock === "b0001".U & arbCnt === "b0001".U) -> sampleReg(3),
-  }
+    (arbLock === "b0001".U & arbCnt === "b0010".U) -> sampleReg(0),
+    (arbLock === "b0001".U & arbCnt === "b0100".U) -> sampleReg(1),
+    (arbLock === "b0001".U & arbCnt === "b1000".U) -> sampleReg(2),
+
+    (arbLock === "b0010".U & arbCnt === "b0001".U) -> sampleReg(2),
+    (arbLock === "b0010".U & arbCnt === "b0010".U) -> sampleReg(3),
+    (arbLock === "b0010".U & arbCnt === "b0100".U) -> sampleReg(0),
+    (arbLock === "b0010".U & arbCnt === "b1000".U) -> sampleReg(1),
+
+    (arbLock === "b0100".U & arbCnt === "b0001".U) -> sampleReg(1),
+    (arbLock === "b0100".U & arbCnt === "b0010".U) -> sampleReg(2),
+    (arbLock === "b0100".U & arbCnt === "b0100".U) -> sampleReg(3),
+    (arbLock === "b0100".U & arbCnt === "b1000".U) -> sampleReg(0),
+
+    (arbLock === "b1000".U & arbCnt === "b0001".U) -> sampleReg(0),
+    (arbLock === "b1000".U & arbCnt === "b0010".U) -> sampleReg(1),
+    (arbLock === "b1000".U & arbCnt === "b0100".U) -> sampleReg(2),
+    (arbLock === "b1000".U & arbCnt === "b1000".U) -> sampleReg(3),
+  ))
+
+
+  val syncSerDat = ShiftRegister( asyncSerDat, 2 )
+
+
 
-  val syncSerDat = 
-    Mux1H( (0 until sampleRate).map{ i => (( arbSel === i.U ) -> ShiftRegister( sampleReg(i), 2) ) } )
     
 }
 
@@ -50,7 +86,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
   def HeaderByte: Int = 8
 
-  val ETH_PRE = "h5A".U(8.W)
+  val ETH_PRE = "h55".U(8.W)
   val ETH_SFD = "hD5".U(8.W)
 
   val STATE_IDLE = 0.U
@@ -68,44 +104,46 @@ trait CDRInAxis{ this: CDRInBase =>
   val crcOut = crcUnit.io.crc
   val crcCmp = Reg(UInt(32.W))
 
-  val bitCnt = Reg(UInt(3.W))
+  val bitCnt = Reg(UInt(4.W))
   val byteCnt = RegInit(0.U(12.W))
 
   val syncSerDat: Bool
-  val checkSFD = RegInit( 0.U(16.W) ); checkSFD := Cat( checkSFD(14,0), syncSerDat )
+  val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
 
-  val shiftData = checkSFD(7,0) //RegInit(0.U(8.W)); shiftData := Cat(shiftData(6,0), syncSerDat)
+  val shiftData = Dualb4b5Decoder(checkSFD(9,0))
 
   val payloadLen = Reg(UInt(12.W))
-  when( byteCnt === 0.U & bitCnt === 7.U & stateCurr === STATE_HEADER ){
+  when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
     payloadLen := Cat( shiftData, 0.U(4.W) )
-  } .elsewhen( byteCnt === 1.U & bitCnt === 7.U & stateCurr === STATE_HEADER ){
+  } .elsewhen( byteCnt === 1.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
     payloadLen := Cat( payloadLen(11,4), shiftData(7,4) )
   }
   
-  val isArbLock: Bool
-
   stateNext := 
     Mux1H(Seq(
-      (stateCurr === STATE_IDLE)    -> ( Mux( isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
+      (stateCurr === STATE_IDLE)    -> ( Mux( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)), STATE_HEADER, STATE_IDLE )), //IDLE
-      (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_HEADER ) ),
+      (stateCurr === STATE_HEADER)  -> ( Mux( (byteCnt === (HeaderByte-1).U)   & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
-      (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U)  ) & (bitCnt === 7.U), STATE_CRC, STATE_PAYLOAD  )), // PAYLOAD
+      (stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen-1.U)  ) & (bitCnt === 9.U), STATE_CRC, STATE_PAYLOAD  )), // PAYLOAD
-      (stateCurr === STATE_CRC)     -> ( Mux( (byteCnt === 3.U)            & (bitCnt === 7.U), STATE_IDLE, STATE_CRC )), //CRC
+      (stateCurr === STATE_CRC)     -> ( Mux( (byteCnt === 3.U)                & (bitCnt === 9.U), STATE_IDLE, STATE_CRC )), //CRC
     ))
 
 
 
 
 
-  when( stateCurr === STATE_IDLE & isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD) ){ //first align
+  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
     bitCnt := 0.U
   } .otherwise{
-    bitCnt := bitCnt + 1.U
+    when( bitCnt === 9.U ){
+      bitCnt := 0.U
+    } .otherwise{
+      bitCnt := bitCnt + 1.U
+    }
   }
 
-  when( stateCurr === STATE_IDLE & isArbLock & checkSFD === Cat(ETH_PRE , ETH_SFD) ){ //first align
+  when( stateCurr === STATE_IDLE & ( checkSFD === Cat(Dualb4b5Encoder(ETH_PRE) , Dualb4b5Encoder(ETH_SFD)) ) ){ //first align
     byteCnt := 0.U
-  } .elsewhen( bitCnt === 7.U ){
+  } .elsewhen( bitCnt === 9.U ){
     when( stateCurr === STATE_HEADER ){
       byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
       assert( byteCnt <= (HeaderByte-1).U )
@@ -123,9 +161,9 @@ trait CDRInAxis{ this: CDRInBase =>
 
 
   val axis_valid = RegInit(false.B)
-  val axis_tdata = RegEnable( shiftData, bitCnt === 7.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
+  val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) )
-  val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )),  bitCnt === 7.U )
+  val axis_tuser = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U & (crcOut =/= ~Cat( shiftData, crcCmp(31,8) )),  bitCnt === 9.U )
-  val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U,                                                 bitCnt === 7.U )
+  val axis_tlast = RegEnable( stateCurr === STATE_CRC & byteCnt === 3.U,                                                 bitCnt === 9.U )
 
   io.axis.valid := axis_valid
   io.axis.bits.tdata := axis_tdata
@@ -135,16 +173,16 @@ trait CDRInAxis{ this: CDRInBase =>
 
   when( io.axis.fire ){
     axis_valid := false.B
-  } .elsewhen( bitCnt === 7.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
+  } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD | stateCurr === STATE_CRC ) ){
     axis_valid := true.B
   }
 
-  when( stateCurr === STATE_CRC & bitCnt === 7.U ){
+  when( stateCurr === STATE_CRC & bitCnt === 9.U ){
     crcCmp := Cat( shiftData, crcCmp(31,8) )
   }
 
 
-  crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 7.U )
+  crcUnit.io.isEnable := ((stateCurr === STATE_HEADER ) | (stateCurr === STATE_PAYLOAD )) & ( bitCnt === 9.U )
   crcUnit.io.dataIn   := shiftData
   
   crcUnit.reset := reset.asBool | ( stateCurr === STATE_IDLE ) //idle

src/main/scala/backBoard/ebus/CDROut.scala

@@ -28,14 +28,14 @@ class CDROut extends Module{
   def STATE_FCS = 3.U
 
 
-  val ETH_PRE = "h5A".U
+  val ETH_PRE = "h55".U
   val ETH_SFD = "hD5".U
 
   val stateNext = Wire(UInt(2.W))
   val stateCurr = RegNext( stateNext, 0.U )
 
 
-  val bitCnt = Reg(UInt(3.W))
+  val bitCnt = Reg(UInt(4.W))
   val byteCnt = Reg(UInt(3.W)) //payload dont need to count
 
   val crcOut = crcUnit.io.crc
@@ -45,18 +45,18 @@ class CDROut extends Module{
   crcUnit.io.dataIn   := io.axis.bits.tdata
   crcUnit.io.isEnable := io.axis.fire
 
-  val shiftData = RegInit(0.U(8.W))
+  val shiftData = RegInit(0.U(10.W))
 
   stateNext := Mux1H(Seq(
     (stateCurr === STATE_IDLE)     -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
-    (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_PREAMBLE )),
+    (stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )),
     (stateCurr === STATE_PAYLOAD)  -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
-    (stateCurr === STATE_FCS)      -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 7.U), STATE_IDLE, STATE_FCS )),
+    (stateCurr === STATE_FCS)      -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )),
   ))
 
-  io.serDat := shiftData.extract(7)
+  io.serDat := shiftData.extract(9)
   io.axis.ready :=
-    bitCnt === 7.U & (
+    bitCnt === 9.U & (
       (stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
       (stateCurr === STATE_PAYLOAD)
     )
@@ -64,24 +64,24 @@ class CDROut extends Module{
 
 
   when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
-    shiftData := ETH_PRE
+    shiftData := Dualb4b5Encoder(ETH_PRE)
   } .otherwise{
-    when( bitCnt =/= 7.U ){
+    when( bitCnt =/= 9.U ){
       shiftData := shiftData << 1
-    } .otherwise{ //bitCnt === 7.U
+    } .otherwise{ //bitCnt === 9.U
       when( stateCurr === STATE_PREAMBLE ){
-        shiftData := MuxCase( ETH_PRE, Array(
+        shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array(
-          ( byteCnt === 6.U ) -> ETH_SFD,
+          ( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD),
-          ( byteCnt === 7.U ) -> io.axis.bits.tdata,
+          ( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
         ))
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
-        shiftData := io.axis.bits.tdata
+        shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
       } .elsewhen( stateCurr === STATE_FCS ){
         shiftData := Mux1H(Seq(
-          ( byteCnt === 0.U) -> ~crcOut( 7,0),
+          ( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ),
-          ( byteCnt === 1.U) -> ~crcOut(15,8),
+          ( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ),
-          ( byteCnt === 2.U) -> ~crcOut(23,16),
+          ( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)),
-          ( byteCnt === 3.U) -> ~crcOut(31,24),
+          ( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)),
         ))
       }
     }
@@ -91,12 +91,16 @@ class CDROut extends Module{
   when( stateCurr === STATE_IDLE ){ //PRE
     bitCnt := 0.U
   } .otherwise{
+    when( bitCnt === 9.U ){
+      bitCnt := 0.U
+    } .otherwise{
     bitCnt := bitCnt + 1.U
+    }
   }
 
   when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
     byteCnt := 0.U
-  } .elsewhen( bitCnt === 7.U ){
+  } .elsewhen( bitCnt === 9.U ){
     byteCnt := byteCnt + 1.U
   }
 

src/main/scala/backBoard/ebus/b4b5.scala

@@ -0,0 +1,65 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+
+object b4b5Encoder{
+  def apply( enq: UInt ): UInt = {
+    Mux1H(Seq(
+      (enq === "b0000".U) -> "b11110".U(5.W),
+      (enq === "b0001".U) -> "b01001".U(5.W),
+      (enq === "b0010".U) -> "b10100".U(5.W),
+      (enq === "b0011".U) -> "b10101".U(5.W),
+      (enq === "b0100".U) -> "b01010".U(5.W),
+      (enq === "b0101".U) -> "b01011".U(5.W),
+      (enq === "b0110".U) -> "b01110".U(5.W),
+      (enq === "b0111".U) -> "b01111".U(5.W),
+      (enq === "b1000".U) -> "b10010".U(5.W),
+      (enq === "b1001".U) -> "b10011".U(5.W),
+      (enq === "b1010".U) -> "b10110".U(5.W),
+      (enq === "b1011".U) -> "b10111".U(5.W),
+      (enq === "b1100".U) -> "b11010".U(5.W),
+      (enq === "b1101".U) -> "b11011".U(5.W),
+      (enq === "b1110".U) -> "b11100".U(5.W),
+      (enq === "b1111".U) -> "b11101".U(5.W),      
+    ))
+  }
+}
+
+object b4b5Decoder{
+  def apply( enq: UInt ): UInt = {
+    Mux1H(Seq(
+      (enq === "b11110".U) -> "b0000".U(4.W),
+      (enq === "b01001".U) -> "b0001".U(4.W),
+      (enq === "b10100".U) -> "b0010".U(4.W),
+      (enq === "b10101".U) -> "b0011".U(4.W),
+      (enq === "b01010".U) -> "b0100".U(4.W),
+      (enq === "b01011".U) -> "b0101".U(4.W),
+      (enq === "b01110".U) -> "b0110".U(4.W),
+      (enq === "b01111".U) -> "b0111".U(4.W),
+      (enq === "b10010".U) -> "b1000".U(4.W),
+      (enq === "b10011".U) -> "b1001".U(4.W),
+      (enq === "b10110".U) -> "b1010".U(4.W),
+      (enq === "b10111".U) -> "b1011".U(4.W),
+      (enq === "b11010".U) -> "b1100".U(4.W),
+      (enq === "b11011".U) -> "b1101".U(4.W),
+      (enq === "b11100".U) -> "b1110".U(4.W),
+      (enq === "b11101".U) -> "b1111".U(4.W),
+    ))
+  }
+}
+
+object Dualb4b5Encoder{
+  def apply( enq: UInt ): UInt = {
+    require( enq.width == 8 )
+    Cat( b4b5Encoder(enq(7,4)),  b4b5Encoder(enq(3,0)) )
+  }
+}
+
+object Dualb4b5Decoder{
+  def apply( enq: UInt ): UInt = {
+    require( enq.width == 10 )
+    Cat( b4b5Decoder(enq(9,5)),  b4b5Decoder(enq(5,0)) )
+  }
+}