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使用4b/5b加跳变时钟选择法升级CDR

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This commit is contained in:
RuigeLee
2025-01-09 17:21:10 +08:00
parent 6584c171d5
commit 404c973671
3 changed files with 163 additions and 56 deletions
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42
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -28,14 +28,14 @@ class CDROut extends Module{
def STATE_FCS = 3.U
val ETH_PRE = "h5A".U
val ETH_PRE = "h55".U
val ETH_SFD = "hD5".U
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, 0.U )
val bitCnt = Reg(UInt(3.W))
val bitCnt = Reg(UInt(4.W))
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val crcOut = crcUnit.io.crc
@@ -45,18 +45,18 @@ class CDROut extends Module{
crcUnit.io.dataIn := io.axis.bits.tdata
crcUnit.io.isEnable := io.axis.fire
val shiftData = RegInit(0.U(8.W))
val shiftData = RegInit(0.U(10.W))
stateNext := Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( io.axis.valid, STATE_PREAMBLE, STATE_IDLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 7.U), STATE_PAYLOAD, STATE_PREAMBLE )),
(stateCurr === STATE_PREAMBLE) -> ( Mux( (byteCnt === 7.U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_PREAMBLE )),
(stateCurr === STATE_PAYLOAD) -> ( Mux( io.axis.fire, Mux( io.axis.bits.tlast, STATE_FCS, STATE_PAYLOAD ), STATE_PAYLOAD ) ),
(stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 7.U), STATE_IDLE, STATE_FCS )),
(stateCurr === STATE_FCS) -> ( Mux( (byteCnt === (3+1).U) & (bitCnt === 9.U), STATE_IDLE, STATE_FCS )),
))
io.serDat := shiftData.extract(7)
io.serDat := shiftData.extract(9)
io.axis.ready :=
bitCnt === 7.U & (
bitCnt === 9.U & (
(stateCurr === STATE_PREAMBLE & byteCnt === 7.U) |
(stateCurr === STATE_PAYLOAD)
)
@@ -64,24 +64,24 @@ class CDROut extends Module{
when( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
shiftData := ETH_PRE
shiftData := Dualb4b5Encoder(ETH_PRE)
} .otherwise{
when( bitCnt =/= 7.U ){
when( bitCnt =/= 9.U ){
shiftData := shiftData << 1
} .otherwise{ //bitCnt === 7.U
} .otherwise{ //bitCnt === 9.U
when( stateCurr === STATE_PREAMBLE ){
shiftData := MuxCase( ETH_PRE, Array(
( byteCnt === 6.U ) -> ETH_SFD,
( byteCnt === 7.U ) -> io.axis.bits.tdata,
shiftData := MuxCase( Dualb4b5Encoder(ETH_PRE), Array(
( byteCnt === 6.U ) -> Dualb4b5Encoder(ETH_SFD),
( byteCnt === 7.U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
))
} .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := io.axis.bits.tdata
shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
} .elsewhen( stateCurr === STATE_FCS ){
shiftData := Mux1H(Seq(
( byteCnt === 0.U) -> ~crcOut( 7,0),
( byteCnt === 1.U) -> ~crcOut(15,8),
( byteCnt === 2.U) -> ~crcOut(23,16),
( byteCnt === 3.U) -> ~crcOut(31,24),
( byteCnt === 0.U) -> Dualb4b5Encoder(~crcOut( 7,0) ),
( byteCnt === 1.U) -> Dualb4b5Encoder(~crcOut(15,8) ),
( byteCnt === 2.U) -> Dualb4b5Encoder(~crcOut(23,16)),
( byteCnt === 3.U) -> Dualb4b5Encoder(~crcOut(31,24)),
))
}
}
@@ -91,12 +91,16 @@ class CDROut extends Module{
when( stateCurr === STATE_IDLE ){ //PRE
bitCnt := 0.U
} .otherwise{
when( bitCnt === 9.U ){
bitCnt := 0.U
} .otherwise{
bitCnt := bitCnt + 1.U
}
}
when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
byteCnt := 0.U
} .elsewhen( bitCnt === 7.U ){
} .elsewhen( bitCnt === 9.U ){
byteCnt := byteCnt + 1.U
}