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人机交互界面完成

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This commit is contained in:
RuigeLee
2023-10-24 17:42:25 +08:00
parent e99ff4789f
commit 3e4964852e
6 changed files with 86 additions and 24 deletions
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39
src/main/scala/Switch/MacRegisters.scala
View File

@@ -69,6 +69,8 @@ class Mac_Config_Bundle extends Bundle{
val r_TxBDNum = Output(UInt(8.W))
val r_TxPauseTV = Output(UInt(16.W))
val r_TxPauseRq = Output(Bool())
}
@@ -77,7 +79,13 @@ class Mac_Config_Bundle extends Bundle{
class MacRegIO extends Mac_Config_Bundle{
val asyncReset = Input(AsyncReset())
val r_TxPtr = Output(UInt(32.W))
val r_RxPtr = Output(UInt(32.W))
val r_TxLen = Output(UInt(16.W))
val r_RxLen = Input(UInt(16.W))
val triTx = Output(Bool())
val triRx = Input(Bool())
}
class MacReg(implicit p: Parameters) extends LazyModule{
@@ -180,7 +188,16 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
when( io.RstTxPauseRq ){ txPauseRq := false.B }
val txPtr = RegInit( "h80002000".U(32.W))
val rxPtr = RegInit( "h80002000".U(32.W))
val txLen = RegInit( 65535.U(16.W))
// val rxLen = RegInit( 65535.U(16.W))
val triRx = RegInit(false.B)
io.r_TxPtr := txPtr
io.r_RxPtr := rxPtr
io.r_TxLen := txLen
when( io.triRx ) { triRx := true.B }
@@ -324,15 +341,31 @@ class MacRegImp(outer: MacReg)(implicit p: Parameters) extends LazyModuleImp(out
)),
( 30 << 2 ) ->
RegFieldGroup("BD", Some("bd"), Seq(
RegField.w(1, RegWriteFn((valid, data) => { io.triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", "bd", reset=Some(0x0)))
RegFieldGroup("DMATrigger", Some("Tx Control DMA"), Seq(
RegField.w(1, RegWriteFn((valid, data) => { io.triTx := (valid & (data === 1.U)) ; true.B} ), RegFieldDesc("bd", "bd", reset=Some(0x0))),
RegField(1, triRx, RegFieldDesc("bd", "bd", reset=Some(0x0))),
)),
( 31 << 2 ) ->
RegFieldGroup("TxRxDMALength", Some("Tx RxControl DMA"), Seq(
RegField(16, txLen, RegFieldDesc("txLen", "length of tx", reset=Some(65535))),
RegField.r(16, io.r_RxLen, RegFieldDesc("rxLen", "length of rx")),
)),
( 32 << 2 ) ->
RegFieldGroup("TxDMAAddress", Some("Tx Control DMA"), Seq(
RegField(32, txPtr, RegFieldDesc("txPtr", "pointer of tx", reset=Some(0x80002000))),
)),
( 33 << 2 ) ->
RegFieldGroup("RxDMAAddress", Some("Rx Control DMA"), Seq(
RegField(32, rxPtr, RegFieldDesc("rxPtr", "pointer of rx", reset=Some(0x80002000))),
)),
)
io.r_RecSmall := RecSmall
io.r_Pad := Pad
io.r_HugEn := HugEn

5
src/main/scala/Switch/RxBuff.scala
View File

@@ -32,11 +32,6 @@ class RxBuffIO extends Bundle{
}
// class Packet_Info_Bundle extends Bundle{
// val LatchedRxLength = UInt(16.W)
// val RxStatusInLatched = UInt(9.W)
// }
class RxBuffBase extends Module{

17
src/main/scala/Switch/Switch.scala
View File

@@ -62,7 +62,22 @@ class SwitchImp(outer: Switch)(implicit p: Parameters) extends LazyModuleImp(out
switchMux.io.txDeq(0) <> mac(0).io.txDeq
switchMux.io.triTx := outer.ethReg.module.io.triTx
switchMux.io.triTx := outer.ethReg.module.io.triTx
outer.ethReg.module.io.triRx := switchMux.io.triRx
switchMux.io.r_TxPtr := outer.ethReg.module.io.r_TxPtr
switchMux.io.r_RxPtr := outer.ethReg.module.io.r_RxPtr
switchMux.io.r_TxLen := outer.ethReg.module.io.r_TxLen
outer.ethReg.module.io.r_RxLen := switchMux.io.r_RxLen

45
src/main/scala/Switch/SwitchMux.scala
View File

@@ -22,6 +22,11 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
val dmaMst = new MacTileLinkMasterIO
val triTx = Input(Bool())
val triRx = Output(Bool())
val r_TxPtr = Input(UInt(32.W))
val r_RxPtr = Input(UInt(32.W))
val r_TxLen = Input(UInt(16.W))
val r_RxLen = Output(UInt(16.W))
val rxEnq = Vec(chn, Flipped(new Receive_Enq_Bundle))
val txDeq = Vec(chn, new Transmit_Bundle)
@@ -53,16 +58,14 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
))
def ptr = "h80002000".U
def txLength = 64.U
def PerPacketCrcEn = true.B
def PerPacketPad = true.B
io.triRx := rxBuff.io.deq.ctrl.fire
io.r_RxLen := RegEnable( rxBuff.io.deq.ctrl.bits.LatchedRxLength, rxBuff.io.deq.ctrl.fire )
rxBuff.io.deq.ctrl.ready := stateCur === stateRx & io.dmaMst.D.fire & isLastD
@@ -70,12 +73,12 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
when( txBuff.io.enq.req.fire ){
txReqValid := false.B
} .elsewhen( io.triTx ){
} .elsewhen( io.triTx & io.r_TxLen > 32.U ){
txReqValid := true.B
}
txBuff.io.enq.req.valid := txReqValid && stateCur === stateIdle
txBuff.io.enq.req.bits.txLength := txLength
txBuff.io.enq.req.bits.txLength := io.r_TxLen
txBuff.io.enq.req.bits.PerPacketCrcEn := PerPacketCrcEn
txBuff.io.enq.req.bits.PerPacketPad := PerPacketPad
@@ -94,8 +97,10 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
val dmaAddress = Reg( UInt(32.W) )
when( stateCur === stateIdle ){
dmaAddress := ptr
when( stateCur === stateIdle & stateNxt === stateTx ){
dmaAddress := io.r_TxPtr
} .elsewhen( stateCur === stateIdle & stateNxt === stateRx ){
dmaAddress := io.r_RxPtr
} .elsewhen( io.dmaMst.A.fire ){
dmaAddress := dmaAddress + 1.U
}
@@ -103,11 +108,19 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
rxBuff.io.deq.data.ready := io.dmaMst.A.fire & (stateCur === stateRx)
assert( ~(rxBuff.io.deq.data.ready & ~rxBuff.io.deq.data.valid) )
rxBuff.io.deq.header.ready := ~io.triTx && ~txReqValid & stateCur === stateIdle
rxBuff.io.deq.header.ready := ~(io.triTx & io.r_TxLen > 32.U) && ~txReqValid & stateCur === stateIdle
when( io.dmaMst.A.fire ){
dmaTxAValid := false.B
} .elsewhen( txBuff.io.enq.req.fire | (stateCur === stateTx & io.dmaMst.D.fire & isLastD & dmaAddress < (ptr + txLength)) ){
} .elsewhen( txBuff.io.enq.req.fire ){
dmaTxAValid := true.B
dmaTxABits :=
edgeOut.Get(
fromSource = 0.U,
toAddress = io.r_TxPtr,
lgSize = log2Ceil(8/8).U,
)._2
} .elsewhen( stateCur === stateTx & io.dmaMst.D.fire & isLastD & dmaAddress < (io.r_TxPtr + io.r_TxLen) ){
dmaTxAValid := true.B
dmaTxABits :=
edgeOut.Get(
@@ -115,7 +128,17 @@ class SwitchMux(edgeOut: TLEdgeOut)(implicit p: Parameters) extends SwitchModule
toAddress = dmaAddress,
lgSize = log2Ceil(8/8).U,
)._2
} .elsewhen( rxBuff.io.deq.header.fire | (stateCur === stateRx & io.dmaMst.D.fire & isLastD & rxBuff.io.deq.data.valid ) ) {
} .elsewhen( rxBuff.io.deq.header.fire ) {
dmaTxAValid := true.B
dmaTxABits :=
edgeOut.Put(
fromSource = 0.U,
toAddress = io.r_RxPtr,
lgSize = log2Ceil(8/8).U,
data = rxBuff.io.deq.data.bits,
mask = "b1".U,
)._2
} .elsewhen( stateCur === stateRx & io.dmaMst.D.fire & isLastD & rxBuff.io.deq.data.valid ) {
dmaTxAValid := true.B
dmaTxABits :=
edgeOut.Put(

2
src/main/scala/Switch/TxBuff.scala
View File

@@ -61,8 +61,6 @@ trait TxBuffEnq{ this: TxBuffBase =>
reqInfo := io.enq.req.bits
} .elsewhen( io.enq.data.fire ){
enqCnt := enqCnt + 1.U
// when( enqCnt + 4.U >= reqInfo.txLength ){
// }
}

2
src/main/scala/Switch/mac/MacTileLinkTx.scala
View File

@@ -29,8 +29,6 @@ class MacTileLinkTxIO extends Bundle{
val TxAbort = Input(Bool()) // Transmit packet abort
val TxDone = Input(Bool()) // Transmission ended
// val TxEndFrm_wb = Input(Bool())
}