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all test pass

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This commit is contained in:
RuigeLee
2023-07-28 20:42:35 +08:00
parent 2048a4d286
commit 3aa4ca17d4
2 changed files with 10 additions and 10 deletions
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10
src/main/scala/backBoard/CDROutBus.scala
View File

@@ -43,18 +43,18 @@ class CDROutBus extends Module{
when( cnt === 0.U ){
when( cnt === 1.U ){
io.dat := true.B
} .elsewhen( cnt >= (0 + 1).U && cnt < (6 + 1).U ){
} .elsewhen( cnt >= (1 + 1).U && cnt < (6 + 1 + 1).U ){
io.dat := address(5)
address := address << 1
} .elsewhen( cnt >= (0 + 1 + 6).U && cnt < (8 + 1 + 6).U ){
} .elsewhen( cnt >= (1 + 1 + 6).U && cnt < (8 + 1+ 1 + 6).U ){
io.dat := register(7)
register := register << 1
} .elsewhen( cnt >= (0 + 1 + 6 + 8).U && cnt < (32 + 1 + 6 + 8).U ){
} .elsewhen( cnt >= (1 + 1 + 6 + 8).U && cnt < (32 + 1 + 1 + 6 + 8).U ){
io.dat := data(31)
data := data << 1
} .elsewhen( cnt >= (0 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 6 + 8 + 32).U ){
} .elsewhen( cnt >= (1 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 1 + 6 + 8 + 32).U ){
io.dat := hash(15)
hash := hash << 1
} .otherwise{

10
tb/sim_backSlv.cpp
View File

@@ -101,19 +101,19 @@ int main(int argc, char **argv, char **env) {
if( main_time == 50000 ){
top->io_req_valid = 1;
top->io_req_bits_address = 0x12;
top->io_req_bits_address = 0x11 << 1 | 0x00;
top->io_req_bits_register = 0x0;
top->io_req_bits_data = 0xaa;
} else if( main_time == 50400 ){
top->io_req_valid = 0;
}
if( main_time == 100000 ){
if( main_time == 150000 ){
top->io_rsp_valid = 1;
top->io_rsp_bits_address = 0x12;
top->io_rsp_bits_address = 0x11 << 1 | 0x00;
top->io_rsp_bits_register = 0x0;
top->io_rsp_bits_data = 0xaa;
} else if( main_time == 100400 ){
} else if( main_time == 150400 ){
top->io_rsp_valid = 0;
}
@@ -127,7 +127,7 @@ int main(int argc, char **argv, char **env) {
main_time ++;
if( main_time > 200000 ){
if( main_time > 250000 ){
break;
}
}