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all test pass

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RuigeLee
2023-07-28 20:42:35 +08:00
parent 2048a4d286
commit 3aa4ca17d4
2 changed files with 10 additions and 10 deletions
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10
src/main/scala/backBoard/CDROutBus.scala
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@@ -43,18 +43,18 @@ class CDROutBus extends Module{
when( cnt === 0.U ){
when( cnt === 1.U ){
io.dat := true.B
} .elsewhen( cnt >= (0 + 1).U && cnt < (6 + 1).U ){
} .elsewhen( cnt >= (1 + 1).U && cnt < (6 + 1 + 1).U ){
io.dat := address(5)
address := address << 1
} .elsewhen( cnt >= (0 + 1 + 6).U && cnt < (8 + 1 + 6).U ){
} .elsewhen( cnt >= (1 + 1 + 6).U && cnt < (8 + 1+ 1 + 6).U ){
io.dat := register(7)
register := register << 1
} .elsewhen( cnt >= (0 + 1 + 6 + 8).U && cnt < (32 + 1 + 6 + 8).U ){
} .elsewhen( cnt >= (1 + 1 + 6 + 8).U && cnt < (32 + 1 + 1 + 6 + 8).U ){
io.dat := data(31)
data := data << 1
} .elsewhen( cnt >= (0 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 6 + 8 + 32).U ){
} .elsewhen( cnt >= (1 + 1 + 6 + 8 + 32).U && cnt < (16 + 1 + 1 + 6 + 8 + 32).U ){
io.dat := hash(15)
hash := hash << 1
} .otherwise{