From 826b35b830722289c7c0206713ef1b66c172f220 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 2 Sep 2025 17:18:25 +0800 Subject: [PATCH 1/8] =?UTF-8?q?=E5=88=A0=E9=99=A4localpoint=E5=92=8Clocalp?= =?UTF-8?q?eroid=E5=92=8C=E4=B8=AD=E6=96=AD2?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 114 ++++-------------- 1 file changed, 25 insertions(+), 89 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 2abc0dc..99079d0 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -99,10 +99,6 @@ class CommonRegisterBundle extends Bundle{ val syncPeroid = UInt(32.W) val recoTimeStamp = UInt(64.W) //时钟补偿寄存器 - val localPeroid = UInt(32.W) - val localPoint = UInt(64.W) - - val custom = Vec( 128, UInt(8.W) ) val smUsedDepth = Vec(8, UInt(8.W)) @@ -480,19 +476,14 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ (addr === "h146".U ) -> cReg.syncOffset(3)(23,16), (addr === "h147".U ) -> cReg.syncOffset(3)(31,24), - (addr === "h148".U ) -> cReg.localPoint(7,0), - (addr === "h149".U ) -> cReg.localPoint(15,8), - (addr === "h14a".U ) -> cReg.localPoint(23,16), - (addr === "h14b".U ) -> cReg.localPoint(31,24), - (addr === "h14c".U ) -> cReg.localPoint(39,32), - (addr === "h14d".U ) -> cReg.localPoint(47,40), - (addr === "h14e".U ) -> cReg.localPoint(55,48), - (addr === "h14f".U ) -> cReg.localPoint(63,56), - - (addr === "h150".U ) -> cReg.localPeroid(7,0), - (addr === "h151".U ) -> cReg.localPeroid(15,8), - (addr === "h152".U ) -> cReg.localPeroid(23,16), - (addr === "h153".U ) -> cReg.localPeroid(31,24), + // (addr === "h148".U ) -> 0.U,//cReg.localPoint(7,0), + // (addr === "h149".U ) -> 0.U,//cReg.localPoint(15,8), + // (addr === "h14a".U ) -> 0.U,//cReg.localPoint(23,16), + // (addr === "h14b".U ) -> 0.U,//cReg.localPoint(31,24), + // (addr === "h14c".U ) -> 0.U,//cReg.localPoint(39,32), + // (addr === "h14d".U ) -> 0.U,//cReg.localPoint(47,40), + // (addr === "h14e".U ) -> 0.U,//cReg.localPoint(55,48), + // (addr === "h14f".U ) -> 0.U,//cReg.localPoint(63,56), ) ++ ( 0 until 128 ).map{ i => @@ -796,8 +787,6 @@ trait InterfaceSync{ this: InterfaceBase => val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid - val localPoint = RegInit(0.U(64.W)); cReg.localPoint := localPoint - val localPeroid = RegInit(0.U(32.W)); cReg.localPeroid := localPeroid val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0 for( i <- 0 until 4 ) { @@ -845,34 +834,23 @@ trait InterfaceSync{ this: InterfaceBase => syncPeroid := Cat( dataw, syncPeroid(23,0) ) } - .elsewhen( addrw === "h148".U ){ - localPoint := Cat( localPoint(63,8), dataw ) - } .elsewhen( addrw === "h149".U ){ - localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) ) - } .elsewhen( addrw === "h14a".U ){ - localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) ) - } .elsewhen( addrw === "h14b".U ){ - localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) ) - } .elsewhen( addrw === "h14c".U ){ - localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) ) - } .elsewhen( addrw === "h14d".U ){ - localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) ) - } .elsewhen( addrw === "h14e".U ){ - localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) ) - } .elsewhen( addrw === "h14f".U ){ - localPoint := Cat( dataw, localPoint(55,0) ) - } - - .elsewhen( addrw === "h150".U ){ - localPeroid := Cat( localPeroid(31,8), dataw ) - } .elsewhen( addrw === "h151".U ){ - localPeroid := Cat( localPeroid(31,16), dataw, localPeroid(7,0) ) - } .elsewhen( addrw === "h152".U ){ - localPeroid := Cat( localPeroid(31,24), dataw, localPeroid(15,0) ) - } .elsewhen( addrw === "h153".U ){ - localPeroid := Cat( dataw, localPeroid(23,0) ) - } - + // .elsewhen( addrw === "h148".U ){ + // localPoint := Cat( localPoint(63,8), dataw ) + // } .elsewhen( addrw === "h149".U ){ + // localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) ) + // } .elsewhen( addrw === "h14a".U ){ + // localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) ) + // } .elsewhen( addrw === "h14b".U ){ + // localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) ) + // } .elsewhen( addrw === "h14c".U ){ + // localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) ) + // } .elsewhen( addrw === "h14d".U ){ + // localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) ) + // } .elsewhen( addrw === "h14e".U ){ + // localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) ) + // } .elsewhen( addrw === "h14f".U ){ + // localPoint := Cat( dataw, localPoint(55,0) ) + // } for( i <- 1 until 4 ){ @@ -932,35 +910,6 @@ trait InterfaceSync{ this: InterfaceBase => syncPeroid := Cat( io.lvds.dataw, syncPeroid(23,0) ) } - .elsewhen( io.lvds.addrw === "h148".U ){ - localPoint := Cat( localPoint(63,8), io.lvds.dataw ) - } .elsewhen( io.lvds.addrw === "h149".U ){ - localPoint := Cat( localPoint(63,16), io.lvds.dataw, localPoint(7,0) ) - } .elsewhen( io.lvds.addrw === "h14a".U ){ - localPoint := Cat( localPoint(63,24), io.lvds.dataw, localPoint(15,0) ) - } .elsewhen( io.lvds.addrw === "h14b".U ){ - localPoint := Cat( localPoint(63,32), io.lvds.dataw, localPoint(23,0) ) - } .elsewhen( io.lvds.addrw === "h14c".U ){ - localPoint := Cat( localPoint(63,40), io.lvds.dataw, localPoint(31,0) ) - } .elsewhen( io.lvds.addrw === "h14d".U ){ - localPoint := Cat( localPoint(63,48), io.lvds.dataw, localPoint(39,0) ) - } .elsewhen( io.lvds.addrw === "h14e".U ){ - localPoint := Cat( localPoint(63,56), io.lvds.dataw, localPoint(47,0) ) - } .elsewhen( io.lvds.addrw === "h14f".U ){ - localPoint := Cat( io.lvds.dataw, localPoint(55,0) ) - } - - .elsewhen( io.lvds.addrw === "h150".U ){ - localPeroid := Cat( localPeroid(31,8), io.lvds.dataw ) - } .elsewhen( io.lvds.addrw === "h151".U ){ - localPeroid := Cat( localPeroid(31,16), io.lvds.dataw, localPeroid(7,0) ) - } .elsewhen( io.lvds.addrw === "h152".U ){ - localPeroid := Cat( localPeroid(31,24), io.lvds.dataw, localPeroid(15,0) ) - } .elsewhen( io.lvds.addrw === "h153".U ){ - localPeroid := Cat( io.lvds.dataw, localPeroid(23,0) ) - } - - for( i <- 1 until 4 ){ when( io.lvds.addrw === ("h13c".U(16.W) + (4*(i-1)).U) ){ syncOffset(i) := Cat( syncOffset(i)(31,8), io.lvds.dataw ) @@ -1040,13 +989,6 @@ trait InterfaceSync{ this: InterfaceBase => io.sync(3) := cReg.syncCfg.extract(3) & syncSign(3) - val isLocalSyncInt = cReg.localPoint === cReg.recoTimeStamp - - when( isLocalSyncInt ){ //时间到达localSync时间点 - localPoint := cReg.localPoint + cReg.localPeroid - } - - } trait InterfaceWdt{ this: InterfaceBase => @@ -1159,11 +1101,6 @@ trait InterfaceSystem{ this: InterfaceBase => intStatus(1) := true.B } - //主站发送周期到了 - val isLocalSyncInt: Bool - when( isLocalSyncInt ){ - intStatus(2) := true.B - } //外部latch中断 val isLatchEvent = @@ -1245,7 +1182,6 @@ trait InterfaceSystem{ this: InterfaceBase => val trigIntPulse = (io.intMstTrig(0) & cReg.intEnable(0)) | //主站发送完成 (io.intMstTrig(1) & cReg.intEnable(1)) | //主站接收完成 - (isLocalSyncInt & cReg.intEnable(2)) | //主站发送周期到了 (isLatchEvent & cReg.intEnable(3)) | //latch Event (isWdtTrigAndEnable & cReg.intEnable(4)) | //主站接收看门狗溢出 (0 until 8).map{ i => io.intSlvTrig(i) & cReg.intEnable(8+i)}.reduce(_|_) | //从站SM请求 From 864a7d3d23e7ce8f87a1e679a0ea771e1f3666e7 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Tue, 2 Sep 2025 18:50:39 +0800 Subject: [PATCH 2/8] =?UTF-8?q?=E5=90=8C=E6=AD=A5=E6=A0=A1=E5=87=86+spi=20?= =?UTF-8?q?lvds=E5=86=99=E5=85=A5=E7=A1=AE=E8=AE=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 64 ++++++++++++------- 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 99079d0..20306e4 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -785,7 +785,8 @@ trait InterfaceSync{ this: InterfaceBase => cReg.syncWidth(i) := syncWidth(i) } - val syncPoint = RegInit(0.U(64.W)); cReg.syncPoint := syncPoint + val syncPoint = RegInit("hFFFFFFFFFFFFFFFF".U(64.W)); cReg.syncPoint := syncPoint + val syncPoint_WRCopy = RegInit("hFFFFFFFFFFFFFFFF".U(64.W)) val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid val syncOffset = for( i <- 0 until 4 ) yield { RegInit(0.U(32.W)) } //空开0 @@ -807,21 +808,22 @@ trait InterfaceSync{ this: InterfaceBase => } when( addrw === "h130".U ){ - syncPoint := Cat( syncPoint(63,8), dataw ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,8), dataw ) } .elsewhen( addrw === "h131".U ){ - syncPoint := Cat( syncPoint(63,16), dataw, syncPoint(7,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,16), dataw, syncPoint_WRCopy(7,0) ) } .elsewhen( addrw === "h132".U ){ - syncPoint := Cat( syncPoint(63,24), dataw, syncPoint(15,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,24), dataw, syncPoint_WRCopy(15,0) ) } .elsewhen( addrw === "h133".U ){ - syncPoint := Cat( syncPoint(63,32), dataw, syncPoint(23,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,32), dataw, syncPoint_WRCopy(23,0) ) } .elsewhen( addrw === "h134".U ){ - syncPoint := Cat( syncPoint(63,40), dataw, syncPoint(31,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,40), dataw, syncPoint_WRCopy(31,0) ) } .elsewhen( addrw === "h135".U ){ - syncPoint := Cat( syncPoint(63,48), dataw, syncPoint(39,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,48), dataw, syncPoint_WRCopy(39,0) ) } .elsewhen( addrw === "h136".U ){ - syncPoint := Cat( syncPoint(63,56), dataw, syncPoint(47,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,56), dataw, syncPoint_WRCopy(47,0) ) } .elsewhen( addrw === "h137".U ){ - syncPoint := Cat( dataw, syncPoint(55,0) ) + syncPoint_WRCopy := Cat( dataw, syncPoint_WRCopy(55,0) ) + syncPoint := Cat( dataw, syncPoint_WRCopy(55,0) ) } .elsewhen( addrw === "h138".U ){ @@ -867,7 +869,6 @@ trait InterfaceSync{ this: InterfaceBase => } - when( io.lvds.isEnW ){ when( io.lvds.addrw === "h120".U ){ @@ -883,21 +884,22 @@ trait InterfaceSync{ this: InterfaceBase => } .elsewhen( io.lvds.addrw === "h130".U ){ - syncPoint := Cat( syncPoint(63,8), io.lvds.dataw ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,8), io.lvds.dataw ) } .elsewhen( io.lvds.addrw === "h131".U ){ - syncPoint := Cat( syncPoint(63,16), io.lvds.dataw, syncPoint(7,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,16), io.lvds.dataw, syncPoint_WRCopy(7,0) ) } .elsewhen( io.lvds.addrw === "h132".U ){ - syncPoint := Cat( syncPoint(63,24), io.lvds.dataw, syncPoint(15,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,24), io.lvds.dataw, syncPoint_WRCopy(15,0) ) } .elsewhen( io.lvds.addrw === "h133".U ){ - syncPoint := Cat( syncPoint(63,32), io.lvds.dataw, syncPoint(23,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,32), io.lvds.dataw, syncPoint_WRCopy(23,0) ) } .elsewhen( io.lvds.addrw === "h134".U ){ - syncPoint := Cat( syncPoint(63,40), io.lvds.dataw, syncPoint(31,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,40), io.lvds.dataw, syncPoint_WRCopy(31,0) ) } .elsewhen( io.lvds.addrw === "h135".U ){ - syncPoint := Cat( syncPoint(63,48), io.lvds.dataw, syncPoint(39,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,48), io.lvds.dataw, syncPoint_WRCopy(39,0) ) } .elsewhen( io.lvds.addrw === "h136".U ){ - syncPoint := Cat( syncPoint(63,56), io.lvds.dataw, syncPoint(47,0) ) + syncPoint_WRCopy := Cat( syncPoint_WRCopy(63,56), io.lvds.dataw, syncPoint_WRCopy(47,0) ) } .elsewhen( io.lvds.addrw === "h137".U ){ - syncPoint := Cat( io.lvds.dataw, syncPoint(55,0) ) + syncPoint_WRCopy := Cat( io.lvds.dataw, syncPoint_WRCopy(55,0) ) + syncPoint := Cat( io.lvds.dataw, syncPoint_WRCopy(55,0) ) } .elsewhen( io.lvds.addrw === "h138".U ){ @@ -923,7 +925,7 @@ trait InterfaceSync{ this: InterfaceBase => } } - cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U(64.W) ) + cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 1.U(64.W) ) cReg.mstDeltaTime := io.mstDeltaTime @@ -938,24 +940,40 @@ trait InterfaceSync{ this: InterfaceBase => val syncOffsetCnt = for( i <- 0 until 4 ) yield { RegInit("hFFFFFFFF".U(32.W)) } //空开第0位 val syncResetCnt = for( i <- 0 until 4 ) yield { RegInit(0.U(16.W)) } //空开第0位 + val recoTimeStamp_Copy = RegInit(1.U(64.W)) - when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点 + + when( + cReg.syncPoint === recoTimeStamp_Copy || + (io.lvds.addrw === "h120".U & io.lvds.isEnW) || //写syncCfg + (io.lvds.addrw === "h137".U & io.lvds.isEnW) || //写syncPoint + (io.lvds.addrw === "h13B".U & io.lvds.isEnW) || //写syncPeroid + (addrw === "h120".U & isEnW) || //写syncCfg + (addrw === "h137".U & isEnW) || //写syncPoint + (addrw === "h13B".U & isEnW) //写syncPeroid + ){ + recoTimeStamp_Copy := cReg.timeStamp + sReg.deltaFinal + } .otherwise{ + recoTimeStamp_Copy := recoTimeStamp_Copy + 1.U + } + + + when( cReg.syncPoint === recoTimeStamp_Copy ){ //时间到达sync0时间点 syncSign(0) := true.B - } .elsewhen( ~cReg.syncCfg(4+0) & syncResetCnt(0) === cReg.syncWidth(0) ){ syncSign(0) := false.B } .elsewhen( cReg.syncCfg(4+0) & isEnW & addrw === "h122".U ){ syncSign(0) := false.B } - when( cReg.syncPoint <= cReg.recoTimeStamp ){ + when( cReg.syncPoint <= recoTimeStamp_Copy ){ syncPoint := syncPoint + cReg.syncPeroid } for( i <- 1 until 4 ) { - when( cReg.syncPoint === cReg.recoTimeStamp ){ //时间到达sync0时间点 + when( cReg.syncPoint === recoTimeStamp_Copy ){ //时间到达sync0时间点 syncOffsetCnt(i) := 0.U } .elsewhen( syncOffsetCnt(i) < cReg.syncOffset(i) ){ syncOffsetCnt(i) := syncOffsetCnt(i) + 1.U From c5d193a1bcc7c1a348a36f58927ac4a58e57c6cf Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 3 Sep 2025 11:23:57 +0800 Subject: [PATCH 3/8] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=B8=BB=E7=AB=99offset?= =?UTF-8?q?=E5=AF=84=E5=AD=98=E5=99=A8=E7=94=A8=E4=BA=8E=E5=A4=9A=E4=B8=AA?= =?UTF-8?q?=E4=B8=BB=E7=AB=99=E6=A0=A1=E5=87=86=E6=97=B6=E9=97=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/Interface.scala | 56 ++++++++++--------- 1 file changed, 30 insertions(+), 26 deletions(-) diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala index 20306e4..1f8ff90 100644 --- a/src/main/scala/backBoard/shin/Interface.scala +++ b/src/main/scala/backBoard/shin/Interface.scala @@ -122,6 +122,7 @@ class MasterRegisterBundle extends Bundle{ val isRecCRCErr = UInt(4.W) val rplTimeStampTx = UInt(16.W) + val timeStampOffset = UInt(64.W) } @@ -476,14 +477,14 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{ (addr === "h146".U ) -> cReg.syncOffset(3)(23,16), (addr === "h147".U ) -> cReg.syncOffset(3)(31,24), - // (addr === "h148".U ) -> 0.U,//cReg.localPoint(7,0), - // (addr === "h149".U ) -> 0.U,//cReg.localPoint(15,8), - // (addr === "h14a".U ) -> 0.U,//cReg.localPoint(23,16), - // (addr === "h14b".U ) -> 0.U,//cReg.localPoint(31,24), - // (addr === "h14c".U ) -> 0.U,//cReg.localPoint(39,32), - // (addr === "h14d".U ) -> 0.U,//cReg.localPoint(47,40), - // (addr === "h14e".U ) -> 0.U,//cReg.localPoint(55,48), - // (addr === "h14f".U ) -> 0.U,//cReg.localPoint(63,56), + (addr === "h148".U ) -> mReg.timeStampOffset(7,0), + (addr === "h149".U ) -> mReg.timeStampOffset(15,8), + (addr === "h14a".U ) -> mReg.timeStampOffset(23,16), + (addr === "h14b".U ) -> mReg.timeStampOffset(31,24), + (addr === "h14c".U ) -> mReg.timeStampOffset(39,32), + (addr === "h14d".U ) -> mReg.timeStampOffset(47,40), + (addr === "h14e".U ) -> mReg.timeStampOffset(55,48), + (addr === "h14f".U ) -> mReg.timeStampOffset(63,56), ) ++ ( 0 until 128 ).map{ i => @@ -785,6 +786,8 @@ trait InterfaceSync{ this: InterfaceBase => cReg.syncWidth(i) := syncWidth(i) } + val timeStampOffset = RegInit(0.U(64.W)); mReg.timeStampOffset := timeStampOffset + val timeStampOffset_WRCopy = RegInit(0.U(64.W)) val syncPoint = RegInit("hFFFFFFFFFFFFFFFF".U(64.W)); cReg.syncPoint := syncPoint val syncPoint_WRCopy = RegInit("hFFFFFFFFFFFFFFFF".U(64.W)) val syncPeroid = RegInit(0.U(32.W)); cReg.syncPeroid := syncPeroid @@ -836,23 +839,24 @@ trait InterfaceSync{ this: InterfaceBase => syncPeroid := Cat( dataw, syncPeroid(23,0) ) } - // .elsewhen( addrw === "h148".U ){ - // localPoint := Cat( localPoint(63,8), dataw ) - // } .elsewhen( addrw === "h149".U ){ - // localPoint := Cat( localPoint(63,16), dataw, localPoint(7,0) ) - // } .elsewhen( addrw === "h14a".U ){ - // localPoint := Cat( localPoint(63,24), dataw, localPoint(15,0) ) - // } .elsewhen( addrw === "h14b".U ){ - // localPoint := Cat( localPoint(63,32), dataw, localPoint(23,0) ) - // } .elsewhen( addrw === "h14c".U ){ - // localPoint := Cat( localPoint(63,40), dataw, localPoint(31,0) ) - // } .elsewhen( addrw === "h14d".U ){ - // localPoint := Cat( localPoint(63,48), dataw, localPoint(39,0) ) - // } .elsewhen( addrw === "h14e".U ){ - // localPoint := Cat( localPoint(63,56), dataw, localPoint(47,0) ) - // } .elsewhen( addrw === "h14f".U ){ - // localPoint := Cat( dataw, localPoint(55,0) ) - // } + .elsewhen( addrw === "h148".U ){ + timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,8), dataw ) + } .elsewhen( addrw === "h149".U ){ + timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,16), dataw, timeStampOffset_WRCopy(7,0) ) + } .elsewhen( addrw === "h14a".U ){ + timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,24), dataw, timeStampOffset_WRCopy(15,0) ) + } .elsewhen( addrw === "h14b".U ){ + timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,32), dataw, timeStampOffset_WRCopy(23,0) ) + } .elsewhen( addrw === "h14c".U ){ + timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,40), dataw, timeStampOffset_WRCopy(31,0) ) + } .elsewhen( addrw === "h14d".U ){ + timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,48), dataw, timeStampOffset_WRCopy(39,0) ) + } .elsewhen( addrw === "h14e".U ){ + timeStampOffset_WRCopy := Cat( timeStampOffset_WRCopy(63,56), dataw, timeStampOffset_WRCopy(47,0) ) + } .elsewhen( addrw === "h14f".U ){ + timeStampOffset_WRCopy := Cat( dataw, timeStampOffset_WRCopy(55,0) ) + timeStampOffset := Cat( dataw, timeStampOffset_WRCopy(55,0) ) + } for( i <- 1 until 4 ){ @@ -931,7 +935,7 @@ trait InterfaceSync{ this: InterfaceBase => sReg.deltaFinal := io.deltaFinal cReg.recoTimeStamp := - Mux(isMstMode, cReg.timeStamp, + Mux(isMstMode, cReg.timeStamp + mReg.timeStampOffset, RegNext( cReg.timeStamp + sReg.deltaFinal, 0.U(64.W) ) ) sReg.slvDeltaTime := io.slvDeltaTime From f0beaf157184e82a5fafff3376fa5ae9594a8e65 Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 3 Sep 2025 12:50:57 +0800 Subject: [PATCH 4/8] =?UTF-8?q?=E6=89=93=E5=BC=80=E5=90=8C=E6=AD=A5?= =?UTF-8?q?=E7=9A=84=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index 087d24a..d87be1f 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -54,8 +54,8 @@ if __name__ == '__main__': #add_tc_2_runlist(sync.tc3()) #add_tc_2_runlist(sync.tc4()) #add_tc_2_runlist(sync.tc5()) - #add_tc_2_runlist(sync.tc6()) - #add_tc_2_runlist(sync.tc7()) + add_tc_2_runlist(sync.tc6()) + add_tc_2_runlist(sync.tc7()) From 5776b9a7adac9b807ad1d8c939358018fb2f818b Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 3 Sep 2025 15:51:28 +0800 Subject: [PATCH 5/8] =?UTF-8?q?=E4=B8=BB=E7=AB=99=E5=8F=91=E9=80=81?= =?UTF-8?q?=E7=9A=84=E5=BA=94=E8=AF=A5=E6=98=AF=E5=8A=A0=E4=BA=86offset?= =?UTF-8?q?=E7=9A=84timestamp=EF=BC=88reco=EF=BC=89=EF=BC=9Bsoftreset?= =?UTF-8?q?=E5=BA=94=E8=AF=A5=E5=90=8C=E6=AD=A5=E5=90=8E=E8=BE=93=E5=85=A5?= =?UTF-8?q?=E5=BC=82=E6=AD=A5=E5=8F=A3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../scala/backBoard/shin/MasterParser.scala | 16 ++++++------- tb/shinTest/ShinTopSpiTb.v | 23 +++++++++++++++---- 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/src/main/scala/backBoard/shin/MasterParser.scala b/src/main/scala/backBoard/shin/MasterParser.scala index eea465e..6bde127 100644 --- a/src/main/scala/backBoard/shin/MasterParser.scala +++ b/src/main/scala/backBoard/shin/MasterParser.scala @@ -113,14 +113,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{ io.downOut.bits.tdata := Mux1H(Seq( ( txCnt < txLen ) -> MuxCase( io.sram_r.datar, Array( - ( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.timeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), - ( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.recoTimeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.recoTimeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.recoTimeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.recoTimeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.recoTimeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.recoTimeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.recoTimeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), + ( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.recoTimeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ), ( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0), ( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8), ( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16), diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 32dc4a7..5210667 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -102,15 +102,28 @@ module ShinTopSpiTb( reg _reset_deactive; wire [(`ALL_DEV_NUM - 1):0] isSoftReset; + reg [(`ALL_DEV_NUM - 1):0] isSoftReset_reg; + + generate + for( genvar i = 0; i < `ALL_DEV_NUM; i = i + 1 ) begin + always @(posedge clock or posedge reset) begin + if(reset) isSoftReset_reg[i] <= 1'b0; + else isSoftReset_reg[i] <= isSoftReset[i]; + end + end + endgenerate + wire [`DEV_NUM:0] io_int_sig; reg latch0; reg latch1; + + ShinTop s_ShinTop_Mst( .clock(clock), - .reset(reset | isSoftReset[0]), + .reset(reset | isSoftReset_reg[0]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), @@ -165,7 +178,7 @@ ShinTop s_ShinTop_Mst( `ifdef DEFINE_SLAVE_DEVICE ShinTop s_ShinTop_slv0( .clock(clock), - .reset(reset | isSoftReset[1]), + .reset(reset | isSoftReset_reg[1]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), @@ -216,7 +229,7 @@ ShinTop s_ShinTop_slv0( ShinTop s_ShinTop_slv1( .clock(clock), - .reset(reset | isSoftReset[2]), + .reset(reset | isSoftReset_reg[2]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), @@ -267,7 +280,7 @@ ShinTop s_ShinTop_slv1( ShinTop s_ShinTop_slv2( .clock(clock), - .reset(reset | isSoftReset[3]), + .reset(reset | isSoftReset_reg[3]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), @@ -318,7 +331,7 @@ ShinTop s_ShinTop_slv2( ShinTop s_ShinTop_slv3( .clock(clock), - .reset(reset | isSoftReset[4]), + .reset(reset | isSoftReset_reg[4]), .io_multiCLK_0(multiCLK[0]), .io_multiCLK_1(multiCLK[1]), From c88046b5eb280affd0bdf5a914c3015f17ca9116 Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 3 Sep 2025 16:01:03 +0800 Subject: [PATCH 6/8] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E6=96=B0=E7=9A=84?= =?UTF-8?q?=E6=B5=8B=E8=AF=95=E7=94=A8=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/gen_pkt.py | 4 +-- tb/shinTest/testcase/sync.py | 52 ++++++++++++++++++++++++++++++++---- 2 files changed, 48 insertions(+), 8 deletions(-) diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py index d87be1f..9f3df70 100755 --- a/tb/shinTest/gen_pkt.py +++ b/tb/shinTest/gen_pkt.py @@ -54,7 +54,7 @@ if __name__ == '__main__': #add_tc_2_runlist(sync.tc3()) #add_tc_2_runlist(sync.tc4()) #add_tc_2_runlist(sync.tc5()) - add_tc_2_runlist(sync.tc6()) + #add_tc_2_runlist(sync.tc6()) add_tc_2_runlist(sync.tc7()) @@ -78,8 +78,6 @@ if __name__ == '__main__': #add_tc_2_runlist(ebmmu.tc17()) #add_tc_2_runlist(ebmmu.tc18()) #add_tc_2_runlist(ebmmu.tc19()) - - #add_tc_2_runlist(watchdog.tc1()) #add_tc_2_runlist(watchdog.tc2()) diff --git a/tb/shinTest/testcase/sync.py b/tb/shinTest/testcase/sync.py index 69ed2a9..5f9b893 100644 --- a/tb/shinTest/testcase/sync.py +++ b/tb/shinTest/testcase/sync.py @@ -1311,18 +1311,60 @@ def tc7(): genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1, True, gen_file_def_ap) - + + genPkt.clean() genPkt.setPktType(0) - sm_idx = 3 + sm_idx = 1 - genPkt.addBeforeExc( "\n#5000\n" + genPkt.addBeforeExc("\n#5000\n" +genIFRwDataCode(0, 0x09, True, 1, [0, ], False, iface=1) +genIFRwDataCode(0, 0x74, False, 4) +genIFRwDataCode(0, 0x40, False, 4) +genIFRwDataCode(0, 0x00, True, 1, [0x1, ]) - +genEnableInsertTimeCode(0xa) + ) + + genPkt.addSubPkt(0x0, 0, 0x180, 0xd, 10, b'\0'*10) + + gen_file_def_ap = gen_file_def + "_rw03" + genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx) + +genWriteTransPktCode(gen_file_def_ap, sm_idx) + +genTrgTransPktCode(gen_file_def_ap, sm_idx) + +genReadAckPktCode(gen_file_def_ap, sm_idx) + + +genMessageCode("--读取中断") + +genIFRwDataCode(0, 0x74, False, 4) + +genIFRwDataCode(1, 0x74, False, 4) + +genIFRwDataCode(2, 0x74, False, 4) + +genIFRwDataCode(3, 0x74, False, 4) + +genIFRwDataCode(4, 0x74, False, 4) + + +genMessageCode("--清除中断") + +genIFRwDataCode(0, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(1, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(2, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(3, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + +genIFRwDataCode(4, 0x78, True, 4, [0xff, 0xff, 0xff, 0xff]) + + +genMessageCode("--读取中断") + +genIFRwDataCode(0, 0x74, False, 4) + +genIFRwDataCode(1, 0x74, False, 4) + +genIFRwDataCode(2, 0x74, False, 4) + +genIFRwDataCode(3, 0x74, False, 4) + +genIFRwDataCode(4, 0x74, False, 4) + +genTcEndFrameCode(gen_file_def) + ) + + genPkt.gen("./generated/shin/%s.vh"%(gen_file_def,), 1, True, gen_file_def_ap) + + + genPkt.clean() + genPkt.setPktType(0) + sm_idx = 1 + + + genPkt.addBeforeExc(genEnableInsertTimeCode(0xa) + '''spi_trans( (16'h0100), (`SPI_READ), (8), (`IF_IDX(0)));\n''' + '''_temp_time = rxBuf[3] + (rxBuf[4] << 8) + (rxBuf[5] << 16) + (rxBuf[6] << 24) + (rxBuf[7] << 32) + (rxBuf[8] << 40) + (rxBuf[9] << 48) + (rxBuf[10] << 56);\n''' + '''_temp_time = _temp_time + 32'h3000;\n\n''' @@ -1456,7 +1498,7 @@ def tc7(): genPkt.addSubPkt(2, 0, 0x120, 0x1, 0x28, data) - gen_file_def_ap = gen_file_def + "_rw03" + gen_file_def_ap = gen_file_def + "_rw04" genPkt.addAfterExc(genWriteTransLenCode(gen_file_def_ap, sm_idx) +genWriteTransPktCode(gen_file_def_ap, sm_idx) +genTrgTransPktCode(gen_file_def_ap, sm_idx) From c14a3a5f4d93f5cbcd1b502164350cfeca0a8877 Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 3 Sep 2025 16:01:50 +0800 Subject: [PATCH 7/8] =?UTF-8?q?=E4=BF=AE=E6=94=B9=E6=B5=8B=E8=AF=95?= =?UTF-8?q?=E7=94=A8=E4=BE=8B=E7=9A=84bug?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/testcase/sync.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tb/shinTest/testcase/sync.py b/tb/shinTest/testcase/sync.py index 5f9b893..9787b2c 100644 --- a/tb/shinTest/testcase/sync.py +++ b/tb/shinTest/testcase/sync.py @@ -1353,7 +1353,6 @@ def tc7(): +genIFRwDataCode(2, 0x74, False, 4) +genIFRwDataCode(3, 0x74, False, 4) +genIFRwDataCode(4, 0x74, False, 4) - +genTcEndFrameCode(gen_file_def) ) genPkt.gen("./generated/shin/%s.vh"%(gen_file_def,), 1, True, gen_file_def_ap) From 790216d6e9fe874ed7bd6c40572666e7ad35381b Mon Sep 17 00:00:00 2001 From: bacon Date: Wed, 3 Sep 2025 16:21:37 +0800 Subject: [PATCH 8/8] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E5=A4=8D=E4=BD=8D?= =?UTF-8?q?=E7=94=B5=E8=B7=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- tb/shinTest/testcase/environment.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/shinTest/testcase/environment.py b/tb/shinTest/testcase/environment.py index b55f46b..a072730 100644 --- a/tb/shinTest/testcase/environment.py +++ b/tb/shinTest/testcase/environment.py @@ -180,7 +180,7 @@ def __GenDevice(id, TerminateNode = False): code_device = ("\tShinTop s_ShinTop_slv%d(\n"%(id, ) +"\t.clock(clock),\n" - +"\t.reset(reset | isSoftReset[%d]),\n\n"%(id + 1,) + +"\t.reset(reset | isSoftReset_reg[%d]),\n\n"%(id + 1,) +"\t.io_multiCLK_0(multiCLK[0]),\n" +"\t.io_multiCLK_1(multiCLK[1]),\n"