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增加resource代码,将spi多合一

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bacon
2026-05-28 19:18:27 +08:00
parent 19cc932896
commit 39986b7039
2 changed files with 574 additions and 0 deletions
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480
src/main/resources/FPGATop_MP_spi.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2025/05/13 11:43:33
// Design Name:
// Module Name: FPGATop
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPGATop(
input clkin,
input resetIn,
input dDatIn_p,
input dDatIn_n,
output dDatOut_p,
output dDatOut_n,
input uDatIn_p,
input uDatIn_n,
output uDatOut_p,
output uDatOut_n,
// input dDatIn,
// output dDatOut,
// input uDatIn,
// output uDatOut,
output sync0,
output sync1,
input latch0,
input latch1,
//input spi_sck,
//input spi_mosi,
//output spi_miso,
//input spi_csn,
input io_qspi_sck,
inout [3:0] io_qspi_data,
input io_qspi_csn,
output interrupt,
output [3:0] io_led,
output [11:0] testIO
);
(* keep="true" *) wire [15:0] multiCLK;
(* keep="true" *) wire [3:0] div4CLK;
//assign testIO = multiCLK;
wire reset;
wire dDatIn;
wire dDatOut;
wire uDatIn;
wire uDatOut;
wire spi_sck;
wire spi_mosi;
wire spi_miso;
wire spi_csn;
//wire clkin_bufg;
// BUFG BUFG_inst (
// .O(clkin_bufg), // 1-bit output: Clock output
// .I(clkin) // 1-bit input: Clock input
// );
//clk_wiz_0 i_clk_0
// (
// .clk_out1(multiCLK[0]),
// .clk_out2(multiCLK[1]),
// .clk_out3(multiCLK[2]),
// .clk_out4(multiCLK[3]),
// .clk_out5(multiCLK[4]),
// .clk_in1(clkin_bufg)
// );
//clk_wiz_1 i_clk_1
// (
// .clk_out1(multiCLK[5]),
// .clk_out2(multiCLK[6]),
// .clk_out3(multiCLK[7]),
// .clk_out4(multiCLK[8]),
// .clk_out5(multiCLK[9]),
// .clk_in1(clkin_bufg)
// );
//clk_wiz_2 i_clk_2
// (
// .clk_out1(multiCLK[10]),
// .clk_out2(multiCLK[11]),
// .clk_out3(multiCLK[12]),
// .clk_out4(multiCLK[13]),
// .clk_out5(multiCLK[14]),
// .clk_out6(multiCLK[15]),
// .clk_in1(clkin_bufg)
// );
(* keep="true" *) wire clk320M;
clk_wiz_3 i_clk_3
(
.clk_out1(clk320M),
// .clk_out2(multiCLK[1]),
// .clk_out3(multiCLK[2]),
// .clk_out4(multiCLK[3]),
// .clk_out5(multiCLK[4]),
// .clk_out6(multiCLK[5]),
.clk_in1(clkin)
);
reg [3:0] phaseCnt;
(* keep="true" *) reg [15:0] phaseClk;
generate
for( genvar i = 0; i < 16; i = i+1 ) begin
BUFG BUFG_inst (
.O(multiCLK[i]), // 1-bit output: Clock output
.I(phaseClk[i]) // 1-bit input: Clock input
);
end
endgenerate
always @( posedge clk320M )begin
phaseCnt <= phaseCnt + 4'd1;
if( phaseCnt == 0 ) begin
phaseClk[0] <= 1;
phaseClk[8] <= 0;
end
if( phaseCnt == 1 ) begin
phaseClk[1] <= 1;
phaseClk[9] <= 0;
end
if( phaseCnt == 2 ) begin
phaseClk[2] <= 1;
phaseClk[10] <= 0;
end
if( phaseCnt == 3 ) begin
phaseClk[3] <= 1;
phaseClk[11] <= 0;
end
if( phaseCnt == 4 ) begin
phaseClk[4] <= 1;
phaseClk[12] <= 0;
end
if( phaseCnt == 5 ) begin
phaseClk[5] <= 1;
phaseClk[13] <= 0;
end
if( phaseCnt == 6 ) begin
phaseClk[6] <= 1;
phaseClk[14] <= 0;
end
if( phaseCnt == 7 ) begin
phaseClk[7] <= 1;
phaseClk[15] <= 0;
end
if( phaseCnt == 8 ) begin
phaseClk[8] <= 1;
phaseClk[0] <= 0;
end
if( phaseCnt == 9 ) begin
phaseClk[9] <= 1;
phaseClk[1] <= 0;
end
if( phaseCnt == 10 ) begin
phaseClk[10] <= 1;
phaseClk[2] <= 0;
end
if( phaseCnt == 11 ) begin
phaseClk[11] <= 1;
phaseClk[3] <= 0;
end
if( phaseCnt == 12 ) begin
phaseClk[12] <= 1;
phaseClk[4] <= 0;
end
if( phaseCnt == 13 ) begin
phaseClk[13] <= 1;
phaseClk[5] <= 0;
end
if( phaseCnt == 14 ) begin
phaseClk[14] <= 1;
phaseClk[6] <= 0;
end
if( phaseCnt == 15 ) begin
phaseClk[15] <= 1;
phaseClk[7] <= 0;
end
end
reg [1:0] div4phCnt;
(* keep="true" *) reg [3:0] div4phClk;
generate
for( genvar i = 0; i < 4; i = i+1 ) begin
BUFG BUFG_div4_inst (
.O(div4CLK[i]), // 1-bit output: Clock output
.I(div4phClk[i]) // 1-bit input: Clock input
);
end
endgenerate
always @( posedge clk320M )begin
div4phCnt <= div4phCnt + 2'd1;
if( div4phCnt == 0 ) begin
div4phClk[0] <= 1;
div4phClk[2] <= 0;
end
if( div4phCnt == 1 ) begin
div4phClk[1] <= 1;
div4phClk[3] <= 0;
end
if( div4phCnt == 2 ) begin
div4phClk[2] <= 1;
div4phClk[0] <= 0;
end
if( div4phCnt == 3 ) begin
div4phClk[3] <= 1;
div4phClk[1] <= 0;
end
end
// proc_sys_reset_0 i_proc_sys_reset(
// .slowest_sync_clk(clk50M),
// .ext_reset_in(resetIn),
// .aux_reset_in(1'b0),
// .mb_debug_sys_rst(1'b0),
// .dcm_locked(1'b1),
// .mb_reset(),
// .bus_struct_reset(),
// .peripheral_reset(reset),
// .interconnect_aresetn(),
// .peripheral_aresetn()
// );
assign reset = resetIn;
wire iqspi_sck;
wire [3:0] iqspi_mosi;
wire [3:0] iqspi_miso;
wire iqspi_isDirIn;
wire iqspi_cs;
wire oqspi_sck;
wire [3:0] oqspi_mosi;
wire [3:0] oqspi_miso;
wire oqspi_isDirIn;
wire oqspi_cs;
wire aqspi_sck;
wire [3:0] aqspi_mosi;
wire [3:0] aqspi_miso;
wire aqspi_isDirIn;
wire aqspi_cs;
//wire qspi_sck;
wire [3:0] qspi_mosi;
wire [3:0] qspi_miso;
wire [3:0] isDirIn;
//wire qspi_cs;
wire bqspi_sck;
wire [3:0] bqspi_mosi;
wire [3:0] bqspi_miso;
wire bqspi_isDirIn;
wire bqspi_cs;
wire vqspi_sck;
wire [3:0] vqspi_mosi;
wire [3:0] vqspi_miso;
wire vqspi_isDirIn;
wire vqspi_cs;
wire [2:0] spi_sel;
wire isSoftReset;
wire [7:0] led;
ShinTop i_ShinTop(
.clock(multiCLK[0]),
.reset(reset | isSoftReset),
.io_dDatIn(dDatIn),
.io_dDatOut(dDatOut),
.io_uDatIn(uDatIn),
.io_uDatOut(uDatOut),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
.io_multiCLK_2(multiCLK[2]),
.io_multiCLK_3(multiCLK[3]),
.io_multiCLK_4(multiCLK[4]),
.io_multiCLK_5(multiCLK[5]),
.io_multiCLK_6(multiCLK[6]),
.io_multiCLK_7(multiCLK[7]),
.io_multiCLK_8(multiCLK[8]),
.io_multiCLK_9(multiCLK[9]),
.io_multiCLK_10(multiCLK[10]),
.io_multiCLK_11(multiCLK[11]),
.io_multiCLK_12(multiCLK[12]),
.io_multiCLK_13(multiCLK[13]),
.io_multiCLK_14(multiCLK[14]),
.io_multiCLK_15(multiCLK[15]),
.io_multiCLKDiv4_0(div4CLK[0]),
.io_multiCLKDiv4_1(div4CLK[1]),
.io_multiCLKDiv4_2(div4CLK[2]),
.io_multiCLKDiv4_3(div4CLK[3]),
.io_iqspi_sck(iqspi_sck),
.io_iqspi_mosi(iqspi_mosi),
.io_iqspi_miso(iqspi_miso),
.io_iqspi_isDirIn(iqspi_isDirIn),
.io_iqspi_csn(iqspi_cs),
.io_aqspi_sck(aqspi_sck),
.io_aqspi_mosi(aqspi_mosi),
.io_aqspi_miso(aqspi_miso),
.io_aqspi_isDirIn(aqspi_isDirIn),
.io_aqspi_csn(aqspi_cs),
.io_bqspi_sck(bqspi_sck),
.io_bqspi_mosi(bqspi_mosi),
.io_bqspi_miso(bqspi_miso),
.io_bqspi_isDirIn(bqspi_isDirIn),
.io_bqspi_csn(bqspi_cs),
.io_vqspi_sck(vqspi_sck),
.io_vqspi_mosi(vqspi_mosi),
.io_vqspi_miso(vqspi_miso),
.io_vqspi_isDirIn(vqspi_isDirIn),
.io_vqspi_csn(vqspi_cs),
.io_ospi_sck(spi_sck),
.io_ospi_mosi(spi_mosi),
.io_ospi_miso(spi_miso),
.io_ospi_csn(spi_csn),
.io_oqspi_sck(oqspi_sck),
.io_oqspi_mosi(oqspi_mosi),
.io_oqspi_miso(oqspi_miso),
.io_oqspi_isDirIn(oqspi_isDirIn),
.io_oqspi_csn(oqspi_cs),
.io_spiSel(spi_sel),
.io_iSync_0(sync0),
.io_iSync_1(sync1),
.io_iSync_2(),
.io_iSync_3(),
.io_isSoftReset(isSoftReset),
//.io_ledTest(led),
.io_interrupt(interrupt),
.io_latchPin_0(latch0),
.io_latchPin_1(latch1),
//.io_testIO(testIO),
.io_hwSerial(48'h4c5850303031)
);
assign io_led = led[5:2];
assign testIO = 12'hfff;
assign iqspi_sck = (spi_sel == 3'b000)? io_qspi_sck : 1'b0;
assign spi_sck = (spi_sel == 3'b001)? io_qspi_sck : 1'b0;
assign oqspi_sck = (spi_sel == 3'b010)? io_qspi_sck : 1'b0;
assign aqspi_sck = (spi_sel == 3'b011)? io_qspi_sck : 1'b0;
assign vqspi_sck = (spi_sel == 3'b100)? io_qspi_sck : 1'b0;
assign bqspi_sck = (spi_sel == 3'b101)? io_qspi_sck : 1'b0;
assign iqspi_mosi = (spi_sel == 3'b000)? qspi_mosi : 4'b0;
assign spi_mosi = (spi_sel == 3'b001)? qspi_mosi[0] : 4'b0;
assign oqspi_mosi = (spi_sel == 3'b010)? qspi_mosi : 4'b0;
assign aqspi_mosi = (spi_sel == 3'b011)? qspi_mosi : 4'b0;
assign vqspi_mosi = (spi_sel == 3'b100)? qspi_mosi : 4'b0;
assign bqspi_mosi = (spi_sel == 3'b101)? qspi_mosi : 4'b0;
assign qspi_miso = (spi_sel == 3'b000)? iqspi_miso :
(spi_sel == 3'b001)? {2'b0, spi_miso, 1'b0} :
(spi_sel == 3'b010)? oqspi_miso :
(spi_sel == 3'b011)? aqspi_miso :
(spi_sel == 3'b100)? vqspi_miso : bqspi_miso;
assign iqspi_cs = (spi_sel == 3'b000)? io_qspi_csn : 1'b1;
assign spi_csn = (spi_sel == 3'b001)? io_qspi_csn : 1'b1;
assign oqspi_cs = (spi_sel == 3'b010)? io_qspi_csn : 1'b1;
assign aqspi_cs = (spi_sel == 3'b011)? io_qspi_csn : 1'b1;
assign vqspi_cs = (spi_sel == 3'b100)? io_qspi_csn : 1'b1;
assign bqspi_cs = (spi_sel == 3'b101)? io_qspi_csn : 1'b1;
assign isDirIn = (spi_sel == 3'b000)? {iqspi_isDirIn, iqspi_isDirIn, iqspi_isDirIn, iqspi_isDirIn} :
(spi_sel == 3'b001)? {2'b1, 1'b0, 1'b1} :
(spi_sel == 3'b010)? {oqspi_isDirIn, oqspi_isDirIn, oqspi_isDirIn, oqspi_isDirIn} :
(spi_sel == 3'b011)? {aqspi_isDirIn, aqspi_isDirIn, aqspi_isDirIn, aqspi_isDirIn} :
(spi_sel == 3'b100)? {vqspi_isDirIn, vqspi_isDirIn, vqspi_isDirIn, vqspi_isDirIn} :
{bqspi_isDirIn, bqspi_isDirIn, bqspi_isDirIn, bqspi_isDirIn};
IOBUF QSPI_D0_inst (
.O(qspi_mosi[0]), // Buffer output
.IO(io_qspi_data[0]), // Buffer inout port (connect directly to top-level port)
.I(qspi_miso[0]), // Buffer input
.T(isDirIn[0]) // 3-state enable input, high=input, low=output
);
IOBUF QSPI_D1_inst (
.O(qspi_mosi[1]), // Buffer output
.IO(io_qspi_data[1]), // Buffer inout port (connect directly to top-level port)
.I(qspi_miso[1]), // Buffer input
.T(isDirIn[1]) // 3-state enable input, high=input, low=output
);
IOBUF QSPI_D2_inst (
.O(qspi_mosi[2]), // Buffer output
.IO(io_qspi_data[2]), // Buffer inout port (connect directly to top-level port)
.I(qspi_miso[2]), // Buffer input
.T(isDirIn[2]) // 3-state enable input, high=input, low=output
);
IOBUF QSPI_D3_inst (
.O(qspi_mosi[3]), // Buffer output
.IO(io_qspi_data[3]), // Buffer inout port (connect directly to top-level port)
.I(qspi_miso[3]), // Buffer input
.T(isDirIn[3]) // 3-state enable input, high=input, low=output
);
IBUFDS i_dDatIn (
.O(dDatIn), // Buffer output
.I(dDatIn_p), // Diff_p buffer input (connect directly to top-level port)
.IB(dDatIn_n) // Diff_n buffer input (connect directly to top-level port)
);
IBUFDS i_uDatIn (
.O(uDatIn), // Buffer output
.I(uDatIn_p), // Diff_p buffer input (connect directly to top-level port)
.IB(uDatIn_n) // Diff_n buffer input (connect directly to top-level port)
);
OBUFDS i_dDatOut (
.O(dDatOut_p), // Diff_p output (connect directly to top-level port)
.OB(dDatOut_n), // Diff_n output (connect directly to top-level port)
.I(dDatOut) // Buffer input
);
OBUFDS i_uDatOut (
.O(uDatOut_p), // Diff_p output (connect directly to top-level port)
.OB(uDatOut_n), // Diff_n output (connect directly to top-level port)
.I(uDatOut) // Buffer input
);
endmodule

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src/main/resources/constr_spi.xdc Normal file
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set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports clkin]
#CPUPC8
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports resetIn]
#set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports spi_mosi]
#set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports spi_miso]
#set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports spi_sck]
#set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports spi_csn]
set_property -dict {PACKAGE_PIN F16 IOSTANDARD TMDS_33} [get_ports dDatOut_p]
set_property -dict {PACKAGE_PIN E16 IOSTANDARD TMDS_33} [get_ports dDatIn_p]
set_property -dict {PACKAGE_PIN E13 IOSTANDARD TMDS_33} [get_ports uDatOut_p]
set_property -dict {PACKAGE_PIN F13 IOSTANDARD TMDS_33} [get_ports uDatIn_p]
set_property -dict {IOSTANDARD TMDS_33} [get_ports dDatOut_n]
set_property -dict {IOSTANDARD TMDS_33} [get_ports dDatIn_n]
set_property -dict {IOSTANDARD TMDS_33} [get_ports uDatOut_n]
set_property -dict {IOSTANDARD TMDS_33} [get_ports uDatIn_n]
#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS33} [get_ports dDatOut]
#set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports dDatIn]
#set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports uDatOut]
#set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports uDatIn]
#set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports sync0]
set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports sync0]
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports sync1]
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports latch0]
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS33} [get_ports latch1]
#CPU PC7
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports interrupt]
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports io_qspi_sck]
set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports {io_qspi_data[0]}]
set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS33} [get_ports {io_qspi_data[1]}]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {io_qspi_data[2]}]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS33} [get_ports {io_qspi_data[3]}]
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports io_qspi_csn]
set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {io_led[0]}]
set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports {io_led[1]}]
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports {io_led[2]}]
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports {io_led[3]}]
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports {testIO[0]}]
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS33} [get_ports {testIO[1]}]
set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33} [get_ports {testIO[2]}]
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33} [get_ports {testIO[3]}]
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports {testIO[4]}]
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports {testIO[5]}]
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports {testIO[6]}]
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {testIO[7]}]
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports {testIO[8]}]
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {testIO[9]}]
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33} [get_ports {testIO[10]}]
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports {testIO[11]}]
#set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports {testIO[12]}]
#set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports {testIO[13]}]
#set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33} [get_ports {testIO[14]}]
#set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33} [get_ports {testIO[15]}]
create_clock -period 20.000 -name sys_clk -waveform {0.000 10.000} [get_ports clkin]
create_clock -period 50.000 -name multi0 -waveform {0.000 25.000} [get_nets {multiCLK[0]}]
create_clock -period 50.000 -name multi1 -waveform {3.125 28.125} [get_nets {multiCLK[1]}]
create_clock -period 50.000 -name multi2 -waveform {6.250 31.250} [get_nets {multiCLK[2]}]
create_clock -period 50.000 -name multi3 -waveform {9.375 34.375} [get_nets {multiCLK[3]}]
create_clock -period 50.000 -name multi4 -waveform {12.500 37.500} [get_nets {multiCLK[4]}]
create_clock -period 50.000 -name multi5 -waveform {15.625 40.625} [get_nets {multiCLK[5]}]
create_clock -period 50.000 -name multi6 -waveform {18.750 43.750} [get_nets {multiCLK[6]}]
create_clock -period 50.000 -name multi7 -waveform {21.875 46.875} [get_nets {multiCLK[7]}]
create_clock -period 50.000 -name multi8 -waveform {25.000 50.000} [get_nets {multiCLK[8]}]
create_clock -period 50.000 -name multi9 -waveform {28.125 53.125} [get_nets {multiCLK[9]}]
create_clock -period 50.000 -name multi10 -waveform {31.250 56.250} [get_nets {multiCLK[10]}]
create_clock -period 50.000 -name multi11 -waveform {34.375 59.375} [get_nets {multiCLK[11]}]
create_clock -period 50.000 -name multi12 -waveform {37.500 62.500} [get_nets {multiCLK[12]}]
create_clock -period 50.000 -name multi13 -waveform {40.625 65.625} [get_nets {multiCLK[13]}]
create_clock -period 50.000 -name multi14 -waveform {43.750 68.750} [get_nets {multiCLK[14]}]
create_clock -period 50.000 -name multi15 -waveform {46.875 71.875} [get_nets {multiCLK[15]}]
create_clock -period 100.000 -name sck_async -waveform {0.000 50.000} [get_nets i_ShinTop/aqspi_sck]
set_clock_groups -name async_group -asynchronous -group [get_clocks {multi0 multi1 multi2 multi3 multi4 multi5 multi6 multi7 multi8 multi9 multi10 multi11 multi12 multi13 multi14 multi15 sys_clk}] -group [get_clocks sck_async]
set_input_delay -clock [get_clocks sck_async] -clock_fall -min -20.000 [get_ports -regexp -filter { NAME =~ ".*qspi.*" && DIRECTION == "INOUT" }]
set_input_delay -clock [get_clocks sck_async] -clock_fall -max 20.000 [get_ports -regexp -filter { NAME =~ ".*qspi.*" && DIRECTION == "INOUT" }]