回去调spi模块，临时提交，后续需要审查

src/main/scala/backBoard/ebus/CDRIn.scala

@@ -29,7 +29,7 @@ trait CDRInOverSample{ this: CDRInBase =>
 
   for( i <- 0 until sampleRate ){
     arbShiftData(i) := Cat( arbShiftData(i)(22,0), RegNext(sampleReg(i)) )
-    when( arbShiftData(i) === "h555555".U & ~isArbLock ){
+    when( arbShiftData(i) === "h5A5A5A".U & ~isArbLock ){
       isArbLock := true.B
       arbSel := i.U
     }
@@ -50,7 +50,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
   def HeaderByte: Int = 8
 
-  val ETH_PRE = "h55".U(8.W)
+  val ETH_PRE = "h5A".U(8.W)
   val ETH_SFD = "hD5".U(8.W)
 
   val STATE_IDLE = 0.U

src/main/scala/backBoard/ebus/CDROut.scala

@@ -28,7 +28,7 @@ class CDROut extends Module{
   def STATE_FCS = 3.U
 
 
-  val ETH_PRE = "h55".U
+  val ETH_PRE = "h5A".U
   val ETH_SFD = "hD5".U
 
   val stateNext = Wire(UInt(2.W))

src/main/scala/backBoard/ebus/crc32.scala

@@ -98,43 +98,8 @@ class crc32_8() extends Module{
 
   // val LFSR_POLY = "h4c11db7".U
 
-  val lfsr_c = for( i <- 0 until 32 ) yield Wire(Bool())
-  val lfsr_q = for( i <- 0 until 32 ) yield RegEnable( lfsr_c(i), true.B, io.isEnable )
-  io.crc := Cat( lfsr_q.reverse )
 
-
+  io.crc := "ha1b2c3d4".U
-  lfsr_c( 0) := lfsr_q(24) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(6)
-  lfsr_c( 1) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(6) ^ io.dataIn(7)
-  lfsr_c( 2) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(6) ^ io.dataIn(7)
-  lfsr_c( 3) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(7)
-  lfsr_c( 4) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6)
-  lfsr_c( 5) := lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
-  lfsr_c( 6) := lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
-  lfsr_c( 7) := lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5) ^ io.dataIn(7)
-  lfsr_c( 8) := lfsr_q( 0) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4)
-  lfsr_c( 9) := lfsr_q( 1) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5)
-  lfsr_c(10) := lfsr_q( 2) ^ lfsr_q(24) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ io.dataIn(0) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5)
-  lfsr_c(11) := lfsr_q( 3) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(27) ^ lfsr_q(28) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(3) ^ io.dataIn(4)
-  lfsr_c(12) := lfsr_q( 4) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(6)
-  lfsr_c(13) := lfsr_q( 5) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(29) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(5) ^ io.dataIn(6) ^ io.dataIn(7)
-  lfsr_c(14) := lfsr_q( 6) ^ lfsr_q(26) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(2) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6) ^ io.dataIn(7)
-  lfsr_c(15) := lfsr_q( 7) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(7)
-  lfsr_c(16) := lfsr_q( 8) ^ lfsr_q(24) ^ lfsr_q(28) ^ lfsr_q(29) ^ io.dataIn(0) ^ io.dataIn(4) ^ io.dataIn(5)
-  lfsr_c(17) := lfsr_q( 9) ^ lfsr_q(25) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(1) ^ io.dataIn(5) ^ io.dataIn(6)
-  lfsr_c(18) := lfsr_q(10) ^ lfsr_q(26) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(2) ^ io.dataIn(6) ^ io.dataIn(7)
-  lfsr_c(19) := lfsr_q(11) ^ lfsr_q(27) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(7)
-  lfsr_c(20) := lfsr_q(12) ^ lfsr_q(28) ^ io.dataIn(4)
-  lfsr_c(21) := lfsr_q(13) ^ lfsr_q(29) ^ io.dataIn(5)
-  lfsr_c(22) := lfsr_q(14) ^ lfsr_q(24) ^ io.dataIn(0)
-  lfsr_c(23) := lfsr_q(15) ^ lfsr_q(24) ^ lfsr_q(25) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(1) ^ io.dataIn(6)
-  lfsr_c(24) := lfsr_q(16) ^ lfsr_q(25) ^ lfsr_q(26) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(2) ^ io.dataIn(7)
-  lfsr_c(25) := lfsr_q(17) ^ lfsr_q(26) ^ lfsr_q(27) ^ io.dataIn(2) ^ io.dataIn(3)
-  lfsr_c(26) := lfsr_q(18) ^ lfsr_q(24) ^ lfsr_q(27) ^ lfsr_q(28) ^ lfsr_q(30) ^ io.dataIn(0) ^ io.dataIn(3) ^ io.dataIn(4) ^ io.dataIn(6)
-  lfsr_c(27) := lfsr_q(19) ^ lfsr_q(25) ^ lfsr_q(28) ^ lfsr_q(29) ^ lfsr_q(31) ^ io.dataIn(1) ^ io.dataIn(4) ^ io.dataIn(5) ^ io.dataIn(7)
-  lfsr_c(28) := lfsr_q(20) ^ lfsr_q(26) ^ lfsr_q(29) ^ lfsr_q(30) ^ io.dataIn(2) ^ io.dataIn(5) ^ io.dataIn(6)
-  lfsr_c(29) := lfsr_q(21) ^ lfsr_q(27) ^ lfsr_q(30) ^ lfsr_q(31) ^ io.dataIn(3) ^ io.dataIn(6) ^ io.dataIn(7)
-  lfsr_c(30) := lfsr_q(22) ^ lfsr_q(28) ^ lfsr_q(31) ^ io.dataIn(4) ^ io.dataIn(7)
-  lfsr_c(31) := lfsr_q(23) ^ lfsr_q(29) ^ io.dataIn(5)
 
 
 

src/main/scala/backBoard/pico/TLCDR.scala

@@ -35,8 +35,11 @@ abstract class TLCDRBase()(implicit p: Parameters) extends BackModule {
 
 
 
-  val txFifo = Module(new Queue(UInt(32.W), 8))
+  val txFifo = Module(new Queue(UInt(32.W), 16))
-  val rxFifo = Module(new Queue(UInt(32.W), 8))
+  val rxFifo = Module(new Queue(UInt(32.W), 16))
+
+
+  val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
 
 }
 
@@ -53,7 +56,8 @@ trait TLCDRTx{ this: TLCDRBase =>
   val isTxFull  = ~txFifo.io.enq.ready
 
 
-  val intTxEnd      = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B)
+  val intTxEnd      = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B) 
+  println("Warning, TxEnd no confident\n")
   val intTxFifoFull = ~RegNext(isTxFull, false.B)  & isTxFull
   val intTxFinish   = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast
 
@@ -74,7 +78,8 @@ trait TLCDRTx{ this: TLCDRBase =>
   txFifo.io.deq.ready := 
     Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B )
 
-  txFifo.reset := reset.asBool | isTLWriteTxLen
+  txFifo.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
+  CDROut.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
 
   CDROut.io.axis.bits.tdata := txData.head(8)
 
@@ -90,7 +95,7 @@ trait TLCDRTx{ this: TLCDRBase =>
   CDROut.io.axis.valid := isTxBusy
 
 
-  when( isTLWriteTxLen ){
+  when( isTLWriteTxLen | isTLWriteSoftReset ){
     isTxBusy := false.B
   }.elsewhen( txFifo.io.deq.fire & ~isTxBusy ){
     isTxBusy := true.B
@@ -121,7 +126,6 @@ trait TLCDRTx{ this: TLCDRBase =>
 
 trait TLCDRRx{ this: TLCDRBase => 
 
-  val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
   // val isTLReadRxStatus     = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U )
   val isTLReadRxLen        = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U )
   val isTLReadRxFifo       = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )
@@ -169,6 +173,7 @@ trait TLCDRRx{ this: TLCDRBase =>
   CDRIn.io.axis.ready := true.B
 
   rxFifo.reset := reset.asBool | isTLWriteSoftReset
+  CDRIn.reset  := reset.asBool | isTLWriteSoftReset
 
   rxFifo.io.deq.ready := isTLReadRxFifo
 

tb/sw/src/MstMain.c

@@ -54,7 +54,7 @@ void main()
 	);
 
 
-	while(1){
+
 
 		*cdr_softReset = 1; //复位脉冲
 		*cdr_direct = 0;
@@ -63,29 +63,30 @@ void main()
 		asm volatile ( //timer 2s
 			"1:\n"
 			"rdcycle %0\n"
-			"srli %0, %0, 12\n"
+			// "srli %0, %0, 12\n"
+			"srli %0, %0, 27\n"
 			// "srli %0, %0, 26\n"
 			"andi %0, %0, 0x1\n"
 			"beqz %0, 1b\n"
 			:"+r"(flag)
 		);
 
-		if( led ){
+		// if( led ){
-			*WriteGpio = 0xFFFFFFFF;
+		// 	*WriteGpio = 0xFFFFFFFF;
-			led = 0;
+		// 	led = 0;
-		} else{
+		// } else{
-			*WriteGpio = 0x0;
+		// 	*WriteGpio = 0x0;
-			led = 1;		
+		// 	led = 1;		
-		}
+		// }
 
 
 		//发送下行包头
 		*cdr_txLen = 520; //总长520
-		*cdr_txFifo = (512 << 20) |( 0 << 16) | 0; //负载长度512，操作数0， 参数全0
+		*cdr_txFifo = (512 << 20) |( 0 << 16) | 0x5a5a; //负载长度512，操作数0， 参数全0//测试，防止脱锁
-		*cdr_txFifo = 0;
+		*cdr_txFifo = 0x5a5a5a5a; //测试，防止脱锁
 
 		for( uint32_t i = 0; i < 512/4; i ++ ){
-			*cdr_txFifo = i;
+			*cdr_txFifo = 0xaa5555aa;//测试，防止脱锁
 		}
 
 
@@ -98,7 +99,6 @@ void main()
 			:"+r"(flag)
 		);
 
-
 		*cdr_softReset = 1; //复位脉冲
 		*cdr_direct = 1;    //方向切换上行
 
@@ -162,5 +162,5 @@ void main()
 
 		totNum = (upRecvLen >> 3);
 
-	}
+
 }

tb/sw/src/SlvMain.c

@@ -64,7 +64,7 @@ void main()
 
 
 
-		*WriteGpio = 0x01;
+		// *WriteGpio = 0x01;
 
 		//等待接收开始中断
 		asm volatile (	
@@ -87,7 +87,7 @@ void main()
 		);
 
 
-		*WriteGpio = 0x03;
+		// *WriteGpio = 0x03;
 
 		if( operator == 0 ){
 			
@@ -107,7 +107,7 @@ void main()
 
 
 
-			*WriteGpio = 0x07;
+			// *WriteGpio = 0x07;
 			register uint32_t downSendLen;	
 
 			if(!isLast){
@@ -150,7 +150,7 @@ void main()
 				}
 			}
 
-			*WriteGpio = 0x0f;
+			// *WriteGpio = 0x0f;
 			
 			//CRC
 			asm volatile (
@@ -164,7 +164,7 @@ void main()
 
 
 
-			*WriteGpio = 0x1f;
+			// *WriteGpio = 0x1f;
 
 			//等待接收完成标志
 			asm volatile (
@@ -175,7 +175,7 @@ void main()
 				: "+r"(flag)
 			);
 
-			*WriteGpio = 0x3f;
+			// *WriteGpio = 0x3f;
 
 			if(!isLast){
 				//等待发送完成标志
@@ -188,7 +188,7 @@ void main()
 				);
 			}
 
-			*WriteGpio = 0x7f;
+			// *WriteGpio = 0x7f;
 
 			register uint32_t one = 1;
 			register uint32_t txLen;