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回去调spi模块，临时提交，后续需要审查

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This commit is contained in:
RuigeLee
2024-12-02 15:00:03 +08:00
parent a1e389ecdc
commit 394854cdce
6 changed files with 36 additions and 66 deletions
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17
src/main/scala/backBoard/pico/TLCDR.scala
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@@ -35,8 +35,11 @@ abstract class TLCDRBase()(implicit p: Parameters) extends BackModule {
val txFifo = Module(new Queue(UInt(32.W), 8))
val rxFifo = Module(new Queue(UInt(32.W), 8))
val txFifo = Module(new Queue(UInt(32.W), 16))
val rxFifo = Module(new Queue(UInt(32.W), 16))
val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
}
@@ -53,7 +56,8 @@ trait TLCDRTx{ this: TLCDRBase =>
val isTxFull = ~txFifo.io.enq.ready
val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B)
val intTxEnd = ShiftRegister( CDROut.io.axis.fire & CDROut.io.axis.bits.tlast, 5, false.B, true.B)
println("Warning, TxEnd no confident\n")
val intTxFifoFull = ~RegNext(isTxFull, false.B) & isTxFull
val intTxFinish = CDROut.io.axis.fire & CDROut.io.axis.bits.tlast
@@ -74,7 +78,8 @@ trait TLCDRTx{ this: TLCDRBase =>
txFifo.io.deq.ready :=
Mux( isTxBusy, CDROut.io.axis.fire & txCnt === 3.U, true.B )
txFifo.reset := reset.asBool | isTLWriteTxLen
txFifo.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
CDROut.reset := reset.asBool | isTLWriteTxLen | isTLWriteSoftReset
CDROut.io.axis.bits.tdata := txData.head(8)
@@ -90,7 +95,7 @@ trait TLCDRTx{ this: TLCDRBase =>
CDROut.io.axis.valid := isTxBusy
when( isTLWriteTxLen ){
when( isTLWriteTxLen | isTLWriteSoftReset ){
isTxBusy := false.B
}.elsewhen( txFifo.io.deq.fire & ~isTxBusy ){
isTxBusy := true.B
@@ -121,7 +126,6 @@ trait TLCDRTx{ this: TLCDRBase =>
trait TLCDRRx{ this: TLCDRBase =>
val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
// val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U )
val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U )
val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )
@@ -169,6 +173,7 @@ trait TLCDRRx{ this: TLCDRBase =>
CDRIn.io.axis.ready := true.B
rxFifo.reset := reset.asBool | isTLWriteSoftReset
CDRIn.reset := reset.asBool | isTLWriteSoftReset
rxFifo.io.deq.ready := isTLReadRxFifo