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bug fixed

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This commit is contained in:
RuigeLee
2023-07-04 13:07:33 +08:00
parent fd9bebe897
commit 3886583b2a
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/mac/MacTilelink.scala
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@@ -753,8 +753,8 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
TxFifoClear := (TxAbortPacket | TxRetryPacket)
val tx_fifo = Module( new MacFifo(dw = 32, dp = 16) )
tx_fifo.io.data_in := io.WB_DAT_I
// tx_fifo.io.data_in := (if( !isTileLink ) {io.WB_DAT_I} else { io.slvA.bits.data })
tx_fifo.io.data_in := io.m_wb_dat_i
// tx_fifo.io.data_in := (if( !isTileLink ) {io.m_wb_dat_i} else { io.slvA.bits.data })
tx_fifo.io.write := MasterWbTX & io.m_wb_ack_i
tx_fifo.io.read := ReadTxDataFromFifo_wb & ~TxBufferEmpty
tx_fifo.io.clear := TxFifoClear