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latch事件寄存器编译通过

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This commit is contained in:
Ruige Lee
2025-07-30 15:22:46 +08:00
parent bfb7c05ac4
commit 3818e280ff
2 changed files with 151 additions and 108 deletions
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89
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -12,33 +12,12 @@ class ShinTopIO extends Bundle{
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
// val downIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
// val downOut = Decoupled(new AXIS_Bundle(8))
// val upIn = Flipped( Decoupled(new AXIS_Bundle(8)) )
// val upOut = Decoupled(new AXIS_Bundle(8))
// val qspi =
// val interrupt = Output(Bool())
// val ctrl = Input(UInt(4.W))
val iqspi = new QSPIInterfaceIO
val ospi = new SSPIInterfaceIO
val oqspi = new QSPIInterfaceIO
// val req = Flipped(Valid(new Bundle{
// val txAddr = UInt(15.W)
// val rxAddr = UInt(15.W)
// val length = UInt(12.W)
// }))
val rsp = Valid(new Bundle{
val isError = Bool()
// val length = UInt(12.W)
})
val iSync = Output(Vec(4, Bool()))
@@ -48,6 +27,8 @@ class ShinTopIO extends Bundle{
val ledTest = Output(UInt(8.W))
val interrupt = Output(Bool())
val latchPin = Input(Vec(2, Bool()))
}
@@ -58,11 +39,6 @@ class ShinTopIO extends Bundle{
abstract class ShinTopBase extends Module{
val io: ShinTopIO = IO(new ShinTopIO)
// val CDRIn = for( i <- 0 until 2 ) yield { Module(new CDRIn) }
// val CDROut = for( i <- 0 until 2 ) yield { Module(new CDROut) }
val slaveParser = Module(new SlaveParser )
val masterParser = Module(new MasterParser)
@@ -73,6 +49,8 @@ abstract class ShinTopBase extends Module{
val interface = Module(new Interface)
interface.io.latchPin := io.latchPin
io.ledTest := RegNext( interface.io.cReg.hwVersion(7,0), "h55".U )
io.isSoftReset := interface.io.isSoftReset
@@ -128,6 +106,19 @@ abstract class ShinTopBase extends Module{
Module( new SMUnit(depth = 2) ),
)
val lvdsSMEnq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMEnq := lvdsSMEnq
val lvdsSMDeq = for( i <- 0 until 4 ) yield WireDefault(false.B); interface.io.lvdsSMDeq := lvdsSMDeq
smUnit(0).io.enq := lvdsSMEnq(0)
smUnit(2).io.enq := lvdsSMEnq(1)
smUnit(4).io.enq := lvdsSMEnq(2)
smUnit(6).io.enq := lvdsSMEnq(3)
smUnit(1).io.deq := lvdsSMDeq(0)
smUnit(3).io.deq := lvdsSMDeq(1)
smUnit(5).io.deq := lvdsSMDeq(2)
smUnit(7).io.deq := lvdsSMDeq(3)
smUnit(0).io.sram_r <> interface.io.sram_r(0)
smUnit(2).io.sram_r <> interface.io.sram_r(1)
@@ -153,7 +144,6 @@ abstract class ShinTopBase extends Module{
for( i <- 0 until 8 ){
interface.io.smUsedDepth(i) := smUnit(i).io.cnt
smUnit(i).reset := reset.asBool | interface.io.isSMReset(i)
}
@@ -210,17 +200,6 @@ abstract class ShinTopBase extends Module{
slaveParser.io.sram_r(3).datar := 0.U
masterParser.io.sram_r.datar := 0.U
smUnit(0).io.enq := false.B
smUnit(2).io.enq := false.B
smUnit(4).io.enq := false.B
smUnit(6).io.enq := false.B
smUnit(1).io.deq := false.B
smUnit(3).io.deq := false.B
smUnit(5).io.deq := false.B
smUnit(7).io.deq := false.B
downCDRIn.io.axis.ready := false.B
slaveParser.io.downIn.valid := false.B
slaveParser.io.downIn.bits := 0.U.asTypeOf(new AXIS_Bundle(8))
@@ -265,7 +244,6 @@ abstract class ShinTopBase extends Module{
}
trait ShinTopMaster{ this: ShinTopBase =>
when( interface.io.cReg.modeSel === true.B ){
@@ -277,30 +255,30 @@ trait ShinTopMaster{ this: ShinTopBase =>
when( interface.io.txReq.bits.rxSM === 0.U ){
smUnit(0).io.sram_w := masterParser.io.sram_w
smUnit(0).io.enq := masterParser.io.rxEnq
lvdsSMEnq(0) := masterParser.io.rxEnq
} .elsewhen( interface.io.txReq.bits.rxSM === 1.U ){
smUnit(2).io.sram_w := masterParser.io.sram_w
smUnit(2).io.enq := masterParser.io.rxEnq
lvdsSMEnq(1) := masterParser.io.rxEnq
} .elsewhen( interface.io.txReq.bits.rxSM === 2.U ){
smUnit(4).io.sram_w := masterParser.io.sram_w
smUnit(4).io.enq := masterParser.io.rxEnq
lvdsSMEnq(2) := masterParser.io.rxEnq
} .elsewhen( interface.io.txReq.bits.rxSM === 3.U ){
smUnit(6).io.sram_w := masterParser.io.sram_w
smUnit(6).io.enq := masterParser.io.rxEnq
lvdsSMEnq(3) := masterParser.io.rxEnq
}
when( interface.io.txReq.bits.txSM === 0.U ){
smUnit(1).io.sram_r <> masterParser.io.sram_r
smUnit(1).io.deq := masterParser.io.txDeq
lvdsSMDeq(0) := masterParser.io.txDeq
} .elsewhen( interface.io.txReq.bits.txSM === 1.U ){
smUnit(3).io.sram_r <> masterParser.io.sram_r
smUnit(3).io.deq := masterParser.io.txDeq
lvdsSMDeq(1) := masterParser.io.txDeq
} .elsewhen( interface.io.txReq.bits.txSM === 2.U ){
smUnit(5).io.sram_r <> masterParser.io.sram_r
smUnit(5).io.deq := masterParser.io.txDeq
lvdsSMDeq(2) := masterParser.io.txDeq
} .elsewhen( interface.io.txReq.bits.txSM === 3.U ){
smUnit(7).io.sram_r <> masterParser.io.sram_r
smUnit(7).io.deq := masterParser.io.txDeq
lvdsSMDeq(3) := masterParser.io.txDeq
}
@@ -335,7 +313,6 @@ trait ShinTopSlave{ this: ShinTopBase =>
slaveParser.io.cReg := interface.io.cReg
slaveParser.io.sReg := interface.io.sReg
when( interface.io.cReg.modeSel === false.B ){
smUnit(0).io.sram_w := slaveParser.io.sram_w(0)
smUnit(2).io.sram_w := slaveParser.io.sram_w(1)
@@ -347,15 +324,15 @@ trait ShinTopSlave{ this: ShinTopBase =>
smUnit(5).io.sram_r <> slaveParser.io.sram_r(2)
smUnit(7).io.sram_r <> slaveParser.io.sram_r(3)
smUnit(0).io.enq := slaveParser.io.dSMenq(0)
smUnit(2).io.enq := slaveParser.io.dSMenq(1)
smUnit(4).io.enq := slaveParser.io.dSMenq(2)
smUnit(6).io.enq := slaveParser.io.dSMenq(3)
lvdsSMEnq(0) := slaveParser.io.dSMenq(0)
lvdsSMEnq(1) := slaveParser.io.dSMenq(1)
lvdsSMEnq(2) := slaveParser.io.dSMenq(2)
lvdsSMEnq(3) := slaveParser.io.dSMenq(3)
smUnit(1).io.deq := slaveParser.io.uSMdeq(0)
smUnit(3).io.deq := slaveParser.io.uSMdeq(1)
smUnit(5).io.deq := slaveParser.io.uSMdeq(2)
smUnit(7).io.deq := slaveParser.io.uSMdeq(3)
lvdsSMDeq(0) := slaveParser.io.uSMdeq(0)
lvdsSMDeq(1) := slaveParser.io.uSMdeq(1)
lvdsSMDeq(2) := slaveParser.io.uSMdeq(2)
lvdsSMDeq(3) := slaveParser.io.uSMdeq(3)
interface.io.mstDeltaTime := slaveParser.io.mstDeltaTimeStamp
interface.io.slvDeltaTime := slaveParser.io.slvDeltaTime