this is the last equal commit
This commit is contained in:
RuigeLee
@@ -149,13 +149,12 @@ abstract class MacTileLinkBase extends Module{
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val TxStatus = RegInit(0.U(4.W)) //[14:11]
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val RxStatus = RegInit(0.U(2.W)) //[14:13]
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// Synchronizing TxRetry TxDone_wb TxAbort signal (synchronized to WISHBONE clock)
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val TxStartFrm_wb = RegInit(false.B)
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// Generating delayed signals
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// Synchronizing TxRetry TxDone_wb TxAbort signal (synchronized to WISHBONE clock)
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val TxRetry_wb = ShiftRegisters( io.TxRetry, 3, false.B, true.B )
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val TxAbort_wb = ShiftRegisters( io.TxAbort, 3, false.B, true.B )
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val TxDone_wb = ShiftRegisters( io.TxDone, 3, false.B, true.B )
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@@ -200,7 +199,6 @@ abstract class MacTileLinkBase extends Module{
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val TxDonePulse = Wire(Bool())
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val TxAbortPulse = Wire(Bool())
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val StartRxBDRead = Wire(Bool())
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@@ -216,7 +214,6 @@ abstract class MacTileLinkBase extends Module{
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val WB_ACK_O = Reg(Bool()); io.WB_ACK_O := WB_ACK_O
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val RxStatusIn = Wire(UInt(9.W))
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// Delayed stage signals
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@@ -243,7 +240,6 @@ abstract class MacTileLinkBase extends Module{
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val TxEn_needed = RegInit(false.B)
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val RxEn_needed = RegInit(false.B)
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val StartRxPointerRead = Wire(Bool())
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val RxPointerRead = RegInit(false.B)
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// RX shift ending signals
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@@ -254,11 +250,10 @@ abstract class MacTileLinkBase extends Module{
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val StartShiftWillEnd = Wire(Bool())
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val StartOccured = RegInit(false.B)
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val TxStartFrm_sync2_txclk = Wire(Bool())
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val TxStartFrm_syncb1 = RegNext(TxStartFrm_sync2_txclk, false.B)
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val TxStartFrm_sync_txclk = Wire(Bool())
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val TxStartFrm_syncb1 = RegNext(TxStartFrm_sync_txclk, false.B)
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val TxStartFrm_syncb2 = RegNext(TxStartFrm_syncb1, false.B)
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val TxFifoClear = Wire(Bool())
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@@ -320,39 +315,24 @@ abstract class MacTileLinkBase extends Module{
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// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
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val ReadTxDataFromFifo_tck_txclk = Wire(Bool())
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val ReadTxDataFromFifo_sync1 = RegNext(ReadTxDataFromFifo_tck_txclk, false.B)
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val ReadTxDataFromFifo_sync2 = RegNext(ReadTxDataFromFifo_sync1, false.B)
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val ReadTxDataFromFifo_sync3 = RegNext(ReadTxDataFromFifo_sync2, false.B)
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val ReadTxDataFromFifo_sync = ShiftRegisters( ReadTxDataFromFifo_tck_txclk, 3, false.B, true.B)
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val RxAbortLatched_rxclk = Wire(Bool())
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val RxAbortSync1 = RegNext( RxAbortLatched_rxclk, false.B )
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val RxAbortSync2 = RegNext( RxAbortSync1, false.B )
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val RxAbortSync3 = RegNext( RxAbortSync2, false.B )
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val RxAbortSync4 = RegNext( RxAbortSync3, false.B )
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val RxAbortSync = ShiftRegisters( RxAbortLatched_rxclk, 4, false.B, true.B )
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val SetWriteRxDataToFifo = Wire(Bool())
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val WriteRxDataToFifo_rxclk = Wire(Bool())
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val WriteRxDataToFifoSync1 = RegNext( WriteRxDataToFifo_rxclk, false.B)
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val WriteRxDataToFifoSync2 = RegNext( WriteRxDataToFifoSync1, false.B)
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val WriteRxDataToFifoSync3 = RegNext( WriteRxDataToFifoSync2, false.B)
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val WriteRxDataToFifoSync = ShiftRegisters(WriteRxDataToFifo_rxclk, 3, false.B, true.B)
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val WriteRxDataToFifo_wb = Wire(Bool())
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val LatchedRxStartFrm_rxclk = Wire(Bool())
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val SyncRxStartFrm = RegNext( LatchedRxStartFrm_rxclk, false.B)
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val SyncRxStartFrm_q = RegNext( SyncRxStartFrm, false.B)
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val SyncRxStartFrm_q2 = RegNext( SyncRxStartFrm_q, false.B)
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val SyncRxStartFrm = ShiftRegisters(LatchedRxStartFrm_rxclk, 3, false.B, true.B)
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val RxFifoReset = Wire(Bool())
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val TxError = Wire(Bool())
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val RxError = Wire(Bool())
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val RxStatusWriteLatched = RegInit(false.B)
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val RxStatusWriteLatched_syncb1 = RegNext(io.RxStatusWriteLatched_sync2, false.B)
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val RxStatusWriteLatched_syncb2 = RegNext(RxStatusWriteLatched_syncb1, false.B)
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val RxStatusWriteLatched_syncb = ShiftRegister(io.RxStatusWriteLatched_sync2, 2, false.B, true.B)
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io.m_wb_bte_o := "b00".U // Linear burst
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@@ -841,7 +821,7 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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TxDonePulse := TxDone_wb(1) & ~TxDone_wb(2)
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TxAbortPulse := TxAbort_wb(1) & ~TxAbort_wb(2)
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val TxError = io.TxUnderRun | io.RetryLimit | io.LateCollLatched | io.CarrierSenseLost
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@@ -910,8 +890,8 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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val TxDonePacketBlocked = RegInit(false.B)
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when(
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TxDone_wb(1) & ~tx_burst_en & MasterWbTX & MasterAccessFinished & ~TxDonePacketBlocked |
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TxDone_wb(1) & ~MasterWbTX & ~TxDonePacketBlocked){
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TxDone_wb(1) & ~TxDonePacketBlocked & MasterWbTX & ~tx_burst_en & MasterAccessFinished |
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TxDone_wb(1) & ~TxDonePacketBlocked & ~MasterWbTX ){
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TxDonePacket := true.B
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}.otherwise{
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TxDonePacket := false.B
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@@ -920,8 +900,8 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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when(TxEn & TxEn_q & TxDonePacket_NotCleared){
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TxDonePacket_NotCleared := false.B
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} .elsewhen(
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TxDone_wb(1) & ~tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
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TxDone_wb(1) & ~MasterWbTX & (~TxDonePacketBlocked)){
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TxDone_wb(1) & ~TxDonePacketBlocked & MasterWbTX & ~tx_burst_en & MasterAccessFinished |
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TxDone_wb(1) & ~TxDonePacketBlocked & ~MasterWbTX ){
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TxDonePacket_NotCleared := true.B
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}
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@@ -942,14 +922,9 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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}
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ReadTxDataFromFifo_wb := ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3
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// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
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ReadTxDataFromFifo_wb := ReadTxDataFromFifo_sync(1) & ~ReadTxDataFromFifo_sync(2)
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StartRxBDRead :=
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RxStatusWrite |
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RxAbortSync3 & ~RxAbortSync4 |
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io.r_RxEn & ~r_RxEn_q
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val StartRxBDRead = RxStatusWrite | (RxAbortSync(2) & ~RxAbortSync(3)) | (io.r_RxEn & ~r_RxEn_q)
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// Reading the Rx buffer descriptor
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when(StartRxBDRead & ~RxReady){
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@@ -960,20 +935,17 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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// Reading of the next receive buffer descriptor starts after reception status
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// is written to the previous one.
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// Reading of the next receive buffer descriptor starts after reception status is written to the previous one.
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// Latching READY status of the Rx buffer descriptor
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when(RxPointerRead){
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RxBDReady := false.B
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} .elsewhen(RxEn & RxEn_q & RxBDRead){
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RxBDReady := rxBuffDesc.e// RxBDReady is sampled only once at the beginning
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RxBDReady := rxBuffDesc.e // RxBDReady is sampled only once at the beginning
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}
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// Latching Rx buffer descriptor status
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// Data is avaliable one cycle after the access is started (at that time
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// signal RxEn is not active)
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// Latching Rx buffer descriptor status Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
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when(RxEn & RxEn_q & RxBDRead){
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RxStatus := Cat(rxBuffDesc.irq, rxBuffDesc.wrap)
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}
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@@ -981,14 +953,14 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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// RxReady generation
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when(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~io.r_RxEn & r_RxEn_q){
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when(ShiftEnded | RxAbortSync(1) & ~RxAbortSync(2) | ~io.r_RxEn & r_RxEn_q){
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RxReady := false.B
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} .elsewhen(RxEn & RxEn_q & RxPointerRead){
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RxReady := true.B
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}
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// Reading Rx BD pointer
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StartRxPointerRead := RxBDRead & RxBDReady
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val StartRxPointerRead = RxBDRead & RxBDReady
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// Reading Tx BD Pointer
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when(StartRxPointerRead){
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@@ -1038,22 +1010,18 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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val LastByteIn_rxclk = Wire(Bool())
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val RxByteCnt_rxclk = Wire(UInt(2.W))
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val RxEnableWindow_rxclk = Wire(Bool())
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StartShiftWillEnd := LastByteIn_rxclk | io.RxValid & io.RxEndFrm & RxByteCnt_rxclk.andR & RxEnableWindow_rxclk
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val StartShiftWillEnd = LastByteIn_rxclk | io.RxValid & io.RxEndFrm & RxByteCnt_rxclk.andR & RxEnableWindow_rxclk
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// Indicating start of the reception process
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val ShiftWillEnd_rxclk = Wire(Bool())
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SetWriteRxDataToFifo :=
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val SetWriteRxDataToFifo =
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(io.RxValid & RxReady & ~io.RxStartFrm & RxEnableWindow_rxclk & (RxByteCnt_rxclk.andR)) |
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(io.RxValid & RxReady & io.RxStartFrm & (RxPointerLSB_rst.andR)) |
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(ShiftWillEnd_rxclk & LastByteIn_rxclk & (RxByteCnt_rxclk.andR))
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WriteRxDataToFifo_wb := WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3
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RxFifoReset := SyncRxStartFrm_q & ~SyncRxStartFrm_q2
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val WriteRxDataToFifo_wb = WriteRxDataToFifoSync(1) & ~WriteRxDataToFifoSync(2)
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val RxFifoReset = SyncRxStartFrm(1) & ~SyncRxStartFrm(2)
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val rx_fifo = Module(new MacFifo(dw = 32, dp = 16))
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val RxDataLatched2_rxclk = Wire(UInt(32.W))
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@@ -1097,8 +1065,7 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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RxStatusIn := Cat(io.ReceivedPauseFrm, io.AddressMiss, RxOverrun, io.InvalidSymbol, io.DribbleNibble, io.ReceivedPacketTooBig, io.ShortFrame, io.LatchedCrcError, io.RxLateCollision)
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val RxStatusIn = Cat(io.ReceivedPauseFrm, io.AddressMiss, RxOverrun, io.InvalidSymbol, io.DribbleNibble, io.ReceivedPacketTooBig, io.ShortFrame, io.LatchedCrcError, io.RxLateCollision)
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// Rx overrun
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@@ -1111,16 +1078,15 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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TxError := io.TxUnderRun | io.RetryLimit | io.LateCollLatched | io.CarrierSenseLost
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// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames are aborted when signal r_RecSmall is set to 0 in MODER register.
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// AddressMiss is identifying that a frame was received because of the promiscous mode and is not an error
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RxError := (RxStatusInLatched_rxclk(6,3).orR) | (RxStatusInLatched_rxclk(1,0).orR)
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val RxError = (RxStatusInLatched_rxclk(6,3).orR) | (RxStatusInLatched_rxclk(1,0).orR)
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// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
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when(RxStatusWriteLatched_syncb2){
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when(RxStatusWriteLatched_syncb){
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RxStatusWriteLatched := false.B
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} .elsewhen(RxStatusWrite){
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RxStatusWriteLatched := true.B
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@@ -1164,17 +1130,10 @@ val masterStage = Cat(MasterWbTX, MasterWbRX, (ReadTxDataFromMemory & ~BlockRead
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// Busy Interrupt
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val Busy_IRQ_rck_rxclk = Wire(Bool())
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val Busy_IRQ_sync1 = RegNext(Busy_IRQ_rck_rxclk)
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val Busy_IRQ_sync2 = RegNext(Busy_IRQ_sync1)
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val Busy_IRQ_sync3 = RegNext(Busy_IRQ_sync2)
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val Busy_IRQ_syncb1 = RegNext(Busy_IRQ_sync2, false.B)
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val Busy_IRQ_syncb2 = RegNext(Busy_IRQ_syncb1, false.B)
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val Busy_IRQ_sync = ShiftRegisters(Busy_IRQ_rck_rxclk, 3)
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io.Busy_IRQ := Busy_IRQ_sync2 & ~Busy_IRQ_sync3
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io.Busy_IRQ := Busy_IRQ_sync(1) & ~Busy_IRQ_sync(2)
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}
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@@ -1208,9 +1167,10 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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val BlockingTxStatusWrite_sync1 = RegNext(BlockingTxStatusWrite, false.B)
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val BlockingTxStatusWrite_sync2 = RegNext(BlockingTxStatusWrite_sync1, false.B); BlockingTxStatusWrite_sync2_txclk := BlockingTxStatusWrite_sync2
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val BlockingTxStatusWrite_sync3 = RegNext(BlockingTxStatusWrite_sync2, false.B); BlockingTxStatusWrite_sync3_txclk := BlockingTxStatusWrite_sync3
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// Synchronizing TxStartFrm_wb to MTxClk
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val TxStartFrm_sync1 = RegNext( TxStartFrm_wb, false.B)
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val TxStartFrm_sync2 = RegNext( TxStartFrm_sync1, false.B); TxStartFrm_sync2_txclk := TxStartFrm_sync2
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val TxStartFrm_sync = ShiftRegister( TxStartFrm_wb, 2, false.B, true.B ); TxStartFrm_sync_txclk := TxStartFrm_sync
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val TxStartFrm = RegInit(false.B); io.TxStartFrm := TxStartFrm
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val TxEndFrm = RegInit(false.B); io.TxEndFrm := TxEndFrm
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val TxData = RegInit(0.U(8.W)); io.TxData := TxData
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@@ -1225,9 +1185,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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val TxRetry_q = RegNext( io.TxRetry, false.B)
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val TxUsedData_q = RegNext( io.TxUsedData, false.B)
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val ReadTxDataFromFifo_syncb1 = RegNext( ReadTxDataFromFifo_sync2, false.B)
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val ReadTxDataFromFifo_syncb2 = RegNext( ReadTxDataFromFifo_syncb1, false.B)
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val ReadTxDataFromFifo_syncb3 = RegNext( ReadTxDataFromFifo_syncb2, false.B)
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val ReadTxDataFromFifo_syncb = ShiftRegisters(ReadTxDataFromFifo_sync(1), 3, false.B, true.B)
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// Changes for tx occur every second clock. Flop is used for this manner.
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when( io.TxDone | io.TxAbort | TxRetry_q){
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@@ -1236,9 +1194,9 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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Flop := ~Flop
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}
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when(TxStartFrm_sync2){
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when(TxStartFrm_sync){
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TxStartFrm := true.B
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} .elsewhen(TxUsedData_q | ~TxStartFrm_sync2 & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
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} .elsewhen(TxUsedData_q | ~TxStartFrm_sync & (io.TxRetry & (~TxRetry_q) | io.TxAbort & (~TxAbort_q))){
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TxStartFrm := false.B
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}
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@@ -1266,7 +1224,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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// Tx data selection (latching)
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when( TxStartFrm_sync2 & ~TxStartFrm ){
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when( TxStartFrm_sync & ~TxStartFrm ){
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TxData := Mux1H(Seq(
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( TxPointerLSB === 0.U ) -> TxData_wb(31,24),// Big Endian Byte Ordering
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( TxPointerLSB === 1.U ) -> TxData_wb(23,16),// Big Endian Byte Ordering
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@@ -1288,7 +1246,7 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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// Latching tx data
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when(
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TxStartFrm_sync2 & ~TxStartFrm |
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TxStartFrm_sync & ~TxStartFrm |
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io.TxUsedData & Flop & TxByteCnt === 3.U |
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TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U){
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TxDataLatched := TxData_wb
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@@ -1328,10 +1286,10 @@ trait MacTileLinkTXClk{ this: MacTileLinkBase =>
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TxByteCnt := TxByteCnt + 1.U
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}
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when(TxStartFrm_sync2 & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
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when(TxStartFrm_sync & ~TxStartFrm | io.TxUsedData & Flop & TxByteCnt === 3.U &
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~LastWord | TxStartFrm & io.TxUsedData & Flop & TxByteCnt === 0.U ){
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ReadTxDataFromFifo_tck := true.B
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} .elsewhen(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3){
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} .elsewhen(ReadTxDataFromFifo_syncb(1) & ~ReadTxDataFromFifo_syncb(2)){
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ReadTxDataFromFifo_tck := false.B
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}
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@@ -1385,18 +1343,20 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
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val LastByteIn = RegInit(false.B); LastByteIn_rxclk := LastByteIn
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val ShiftWillEnd = RegInit(false.B); ShiftWillEnd_rxclk := ShiftWillEnd
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val WriteRxDataToFifo = RegInit(false.B); WriteRxDataToFifo_rxclk := WriteRxDataToFifo
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val LatchedRxLength = RegInit(0.U(16.W)); LatchedRxLength_rxclk := LatchedRxLength
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val RxAbortLatched = RegInit(false.B); RxAbortLatched_rxclk := RxAbortLatched
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val RxStatusInLatched = RegInit(0.U(9.W)); RxStatusInLatched_rxclk := RxStatusInLatched
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val LatchedRxLength = RegEnable(io.RxLength, 0.U(16.W), io.LoadRxStatus); LatchedRxLength_rxclk := LatchedRxLength
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val RxStatusInLatched = RegEnable(RxStatusIn, 0.U(9.W), io.LoadRxStatus); RxStatusInLatched_rxclk := RxStatusInLatched
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val ShiftEnded_rck = RegInit(false.B); ShiftEnded_rck_txclk := ShiftEnded_rck
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val ShiftEndedSync_c1 = RegNext( ShiftEndedSync2, false.B)
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val ShiftEndedSync_c2 = RegNext( ShiftEndedSync_c1, false.B)
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val RxAbortSyncb1 = RegNext( RxAbortSync2, false.B)
|
||||
val RxAbortSyncb2 = RegNext( RxAbortSyncb1, false.B)
|
||||
|
||||
val ShiftEndedSync = ShiftRegisters(ShiftEndedSync2, 2, false.B, true.B)
|
||||
|
||||
val RxAbortSyncb = ShiftRegister( RxAbortSync(1), 2, false.B, true.B )
|
||||
|
||||
val RxEnableWindow = RegInit(false.B); RxEnableWindow_rxclk := RxEnableWindow
|
||||
val LatchedRxStartFrm = RegInit(false.B); LatchedRxStartFrm_rxclk := LatchedRxStartFrm
|
||||
val RxStatusWriteLatched_sync1 = RegNext(RxStatusWriteLatched, false.B)
|
||||
val RxStatusWriteLatched_sync2 = RegNext(RxStatusWriteLatched_sync1, false.B); io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync2
|
||||
|
||||
val RxStatusWriteLatched_sync = ShiftRegister(RxStatusWriteLatched, 2, false.B, true.B); io.RxStatusWriteLatched_sync2 := RxStatusWriteLatched_sync
|
||||
// Indicating that last byte is being reveived
|
||||
|
||||
when(ShiftWillEnd & RxByteCnt.andR | io.RxAbort){
|
||||
@@ -1471,14 +1431,14 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
|
||||
|
||||
when(SetWriteRxDataToFifo & ~io.RxAbort){
|
||||
WriteRxDataToFifo := true.B
|
||||
} .elsewhen(WriteRxDataToFifoSync2 | io.RxAbort){
|
||||
} .elsewhen(WriteRxDataToFifoSync(1) | io.RxAbort){
|
||||
WriteRxDataToFifo := false.B
|
||||
}
|
||||
|
||||
|
||||
when(io.RxStartFrm & ~SyncRxStartFrm_q){
|
||||
when(io.RxStartFrm & ~SyncRxStartFrm(1)){
|
||||
LatchedRxStartFrm := true.B
|
||||
} .elsewhen(SyncRxStartFrm_q){
|
||||
} .elsewhen(SyncRxStartFrm(1)){
|
||||
LatchedRxStartFrm := false.B
|
||||
}
|
||||
|
||||
@@ -1486,7 +1446,7 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
|
||||
// Generation of the end-of-frame signal
|
||||
when(~io.RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd){
|
||||
ShiftEnded_rck := true.B
|
||||
} .elsewhen(io.RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2){
|
||||
} .elsewhen(io.RxAbort | ShiftEndedSync(0) & ShiftEndedSync(1)){
|
||||
ShiftEnded_rck := false.B
|
||||
}
|
||||
|
||||
@@ -1498,34 +1458,28 @@ trait MacTileLinkRXClk{ this: MacTileLinkBase =>
|
||||
}
|
||||
|
||||
|
||||
when(RxAbortSyncb2){
|
||||
when(RxAbortSyncb){
|
||||
RxAbortLatched := false.B
|
||||
} .elsewhen(io.RxAbort){
|
||||
RxAbortLatched := true.B
|
||||
}
|
||||
|
||||
when(io.LoadRxStatus){
|
||||
LatchedRxLength := io.RxLength
|
||||
}
|
||||
|
||||
|
||||
when(io.LoadRxStatus){
|
||||
RxStatusInLatched := RxStatusIn
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
val Busy_IRQ_rck = RegInit(false.B); Busy_IRQ_rck_rxclk := Busy_IRQ_rck
|
||||
val Busy_IRQ_syncb = ShiftRegister( Busy_IRQ_sync(1), 2, false.B, true.B )
|
||||
|
||||
when(io.RxValid & io.RxStartFrm & ~RxReady){
|
||||
Busy_IRQ_rck := true.B
|
||||
} .elsewhen(Busy_IRQ_syncb2){
|
||||
} .elsewhen(Busy_IRQ_syncb){
|
||||
Busy_IRQ_rck := false.B
|
||||
}
|
||||
|
||||
when(true.B){
|
||||
Busy_IRQ_syncb1 := Busy_IRQ_sync2
|
||||
Busy_IRQ_syncb2 := Busy_IRQ_syncb1
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user