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spi请求地址大小端翻转

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Ruige Lee
2025-05-28 16:41:32 +08:00
parent 88e65fb364
commit 3721d365ce
2 changed files with 4 additions and 4 deletions
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4
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -89,7 +89,7 @@ abstract class SpiInterfaceBase extends Module{
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrw := exRegi
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrw := Cat(exRegi, addrw(7,0))
addrw := Cat(addrw(7,0), exRegi)
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrw := addrw + 1.U
@@ -101,7 +101,7 @@ abstract class SpiInterfaceBase extends Module{
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 1.U){ //CS为低，且SCK上跳的第0byte
addrr := exRegi
} .elsewhen(isSckPosedgeNext(0) & ~shiftCSn(1) & bitSel === 0.U & byteSel === 2.U) {//CS为低，且SCK上跳的第0byte
addrr := Cat(exRegi, addrr(7,0))
addrr := Cat(addrr(7,0), exRegi)
} .otherwise{ // byteSel > 1.U
when( isSckPosedgeNext(1) & byteSel > 3.U & bitSel === 0.U ){
addrr := addrr + 1.U

4
tb/shinTest/ShinTopSpiTb.v
View File

@@ -439,8 +439,8 @@ end
//sidx为0~4；外部spi为5~9，外部qspi为10~15
task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,input [7:0] sidx );
begin
txBuf[0] <= saddress[7:0];
txBuf[1] <= saddress[15:8];
txBuf[0] <= saddress[15:8];
txBuf[1] <= saddress[7:0];
txBuf[2] <= scmd;
length <= slength + 3;