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处理断言及状态机卡住问题，从这个版本开始，所有断言错误都应该处理；recParser的错误状态会触发5、6号不可屏蔽中断，软件需要清中断然后recParser恢复状态，cdrout溢出问题不再触发中断，该次传输将会发生至少两次错误

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This commit is contained in:
Ruige Lee
2025-05-26 11:52:40 +08:00
parent 5fa5a4c244
commit 370e6b119c
6 changed files with 55 additions and 15 deletions
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5
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -56,7 +56,10 @@ class CDROut extends Module{
(stateCurr === STATE_PAYLOAD)
)
assert( ~(~io.axis.valid & io.axis.ready) )
// assert( ~(~io.axis.valid & io.axis.ready) )
when( ~io.axis.valid & io.axis.ready ){
printf( "Error, CDROut axis overflow!\n" )
}

26
src/main/scala/backBoard/shin/Interface.scala
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@@ -172,6 +172,8 @@ class InterfaceIO extends Bundle{
val isSoftReset = Output(Bool())
val intMstTrig = Input(Vec(2, Bool()))
val intHWTrig = Input(Vec(2, Bool()))
val intHWClr = Output(Vec(2, Bool()))
val intSlvTrig = Input(Vec(8, Bool()))
val interrupt = Output(Bool())
@@ -746,16 +748,15 @@ trait InterfaceSystem{ this: InterfaceBase =>
val intStatus = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
cReg.intStatus := Cat( intStatus.reverse )
val intMstTrig = Input(Vec(2, Bool()))
val intSlvTrig = Input(Vec(8, Bool()))
//主站发送完成
when( io.intMstTrig(0) ){
when( io.intMstTrig(0) & cReg.intEnable(0) ){
intStatus(0) := true.B
}
//主站接收完成
when( io.intMstTrig(1) ){
when( io.intMstTrig(1) & cReg.intEnable(1) ){
intStatus(1) := true.B
}
@@ -764,16 +765,26 @@ trait InterfaceSystem{ this: InterfaceBase =>
//主站接收看门狗溢出
//下行接收硬件错误
when( io.intHWTrig(0) ){
intStatus(5) := true.B
}
when( io.intHWTrig(1) ){
intStatus(6) := true.B
}
//上行接收硬件错误
//从站SM请求
for( i <- 0 until 8 ){
when( io.intSlvTrig(i) ){
when( io.intSlvTrig(i) & cReg.intEnable(8+i)){
intStatus(8+i) := true.B
}
}
//写清中断
for( i <- 0 until 8 ){
when( dataw.extract(i) & isEnW & addrw === "h74".U ){
intStatus(i) := false.B
@@ -783,6 +794,9 @@ trait InterfaceSystem{ this: InterfaceBase =>
}
}
io.intHWClr(0) := dataw.extract(5) & isEnW & addrw === "h74".U
io.intHWClr(1) := dataw.extract(6) & isEnW & addrw === "h74".U
io.interrupt := intStatus.reduce(_|_)
}

9
src/main/scala/backBoard/shin/ShinTop.scala
View File

@@ -253,6 +253,9 @@ abstract class ShinTopBase extends Module{
interface.io.intSlvTrig(6) := false.B
interface.io.intSlvTrig(7) := false.B
interface.io.intHWTrig(0) := false.B
interface.io.intHWTrig(1) := false.B
}
}
@@ -362,8 +365,14 @@ trait ShinTopSlave{ this: ShinTopBase =>
interface.io.intSlvTrig(6) := slaveParser.io.dSMenq(3)
interface.io.intSlvTrig(7) := slaveParser.io.uSMdeq(3)
interface.io.intHWTrig(0) := slaveParser.io.intHWTrig(0)
interface.io.intHWTrig(1) := slaveParser.io.intHWTrig(1)
}
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0)
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1)
interface.io.lvds <> slaveParser.io.lvds
interface.io.localDevIndex := slaveParser.io.localDevIndex

11
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -67,6 +67,9 @@ class SlaveParserIO extends Bundle{
val cReg = Input(new CommonRegisterBundle)
val lvds = new RegAccessInterfaceIO
val intHWTrig = Output(Vec(2, Bool()))
val intHWClr = Input (Vec(2, Bool()))
}
abstract class SlaveParserBase extends Module{
@@ -766,7 +769,13 @@ class SlaveParser extends SlaveParserBase
with SlaveParserIndex
with SlaveParserRW
with SlaveParserSync
with SlaveParserProbe
with SlaveParserProbe{
io.intHWTrig(0) := downRecParser.io.isError
io.intHWTrig(1) := upRecParser.io.isError
downRecParser.io.resp := io.intHWClr(0)
upRecParser.io.resp := io.intHWClr(1)
}

9
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -112,8 +112,13 @@ class SlaveRecParser extends Module{
io.data.valid := io.rec.fire & stateCurr === STATE_PAYLOAD_DATA
io.data.bits := io.rec.bits.tdata
assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was rejected by fifo!" )
// assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was rejected by fifo!" )
val isDataRejErr = io.data.valid & ~io.data.ready
when( (io.data.valid & ~io.data.ready) ){
printf( "Error! Receive Data was rejected by fifo!\n")
}
when( io.rec.fire ){
@@ -171,7 +176,7 @@ class SlaveRecParser extends Module{
Mux( lengthCnt === (8-1).U, STATE_PAYLOAD_DATA, STATE_SUBMSG_HEADER )
), STATE_SUBMSG_HEADER),
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
( stateCurr === STATE_PAYLOAD_DATA ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast | isDataRejErr, STATE_ERROR,
Mux( lengthCnt === ( subMsgHeader.length - 1.U),
Mux( frameLenCnt === frameHeader.frameLenAim - 1.U, STATE_CRC, STATE_SUBMSG_HEADER
), STATE_PAYLOAD_DATA )

10
src/main/scala/backBoard/shin/SlaveSendGen.scala
View File

@@ -40,14 +40,14 @@ class SlaveSendGen extends Module{
val STATE_SUBMSG_HEADER = 2.U
val STATE_SUBMSG_DATA = 3.U
val STATE_CRC = 4.U //CRC校验
val STATE_ERROR = 5.U
//val STATE_ERROR = 5.U
val STATE_WAIT = 6.U
val stateNext = Wire(UInt(3.W))
val stateCurr = RegNext(stateNext, STATE_IDLE); io.stateCurr := stateCurr
io.isError := stateCurr === STATE_ERROR
io.isError := false.B//stateCurr === STATE_ERROR
crc.io.isEnable := io.send.fire & (
stateCurr === STATE_FRAME_HEADER |
@@ -128,7 +128,7 @@ class SlaveSendGen extends Module{
STATE_SUBMSG_DATA
), STATE_SUBMSG_DATA ),
(stateCurr === STATE_CRC) -> Mux( io.send.fire, Mux( lengthCnt === (4-1).U, STATE_IDLE, STATE_CRC ), STATE_CRC),
(stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
// (stateCurr === STATE_ERROR) -> Mux( io.send.fire, STATE_IDLE, STATE_ERROR),
(stateCurr === STATE_WAIT) -> Mux( io.subMsgReq.valid, STATE_SUBMSG_HEADER, STATE_WAIT),
))
@@ -191,8 +191,8 @@ class SlaveSendGen extends Module{
(stateCurr === STATE_CRC) -> tdata_crc,
))
io.send.bits.tuser := (stateCurr === STATE_ERROR & stateNext === STATE_IDLE)
io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE) || (stateCurr === STATE_ERROR & stateNext === STATE_IDLE)
io.send.bits.tuser := false.B//(stateCurr === STATE_ERROR & stateNext === STATE_IDLE)
io.send.bits.tlast := (stateCurr === STATE_CRC & stateNext === STATE_IDLE) //|| (stateCurr === STATE_ERROR & stateNext === STATE_IDLE)